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- research-articleMarch 2023
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction
- Ashish Reddy Bommana,
- Susheel Ujwal Siddamshetty,
- Dhilleswararao Pudi,
- Arvind Thumatti K. R.,
- Srinivas Boppu,
- M Sabarimalai Manikandan,
- Linga Reddy Cenkeramaddi
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 28, Issue 3Article No.: 32, Pages 1–35https://doi.org/10.1145/3567423Energy efficiency has become the new performance criterion in this era of pervasive embedded computing; thus, accelerator-rich multi-processor system-on-chips are commonly used in embedded computing hardware. Once computationally intensive machine ...
- short-paperMay 2016
Extracting Designs of Secure IPs Using FPGA CAD Tools
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSIPages 293–298https://doi.org/10.1145/2902961.2903033In today's competitive market, a company's success is strongly dependent on delivering sophisticated and state-of-the-art IPs prior to their competitors. To take a short cut, a company may resort to reverse engineering or pirating their competitor's IP.
... - research-articleMay 2013
Power gating applied to MP-SoCs for standby-mode power management
DAC '13: Proceedings of the 50th Annual Design Automation ConferenceArticle No.: 158, Pages 1–5https://doi.org/10.1145/2463209.2488930Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional processor cores support both general purpose and graphics optimized processing in mobile SoCs, but ...
- ArticleSeptember 2011
High-speed and low-power PID structures for embedded applications
In embedded control applications, control-rate and energy-consumption are two critical design issues. This paper presents a series of high-speed and lowpower finite-word-length PID controllers based on a new recursive multiplication algorithm. Compared ...
- ArticleJune 2010
An NProd Algorithm IP Design for Real-Time Image Matching Application onto FPGA
ICECE '10: Proceedings of the 2010 International Conference on Electrical and Control EngineeringPages 404–409https://doi.org/10.1109/iCECE.2010.105Real-time image matching is usually a core operation in many embedded applications. Often in such applications, low implementation costs and short time-to-market are required. Field programmable gates array (FPGA) based reconfigurable hardware ...
- research-articleJune 2002
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 10, Issue 3Pages 240–252https://doi.org/10.1109/TVLSI.2002.1043327This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based ...
- ArticleSeptember 2001
Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design
ISSS '01: Proceedings of the 14th international symposium on Systems synthesisPages 233–238https://doi.org/10.1145/500001.500056We propose an Internet-based concurrent-simulation scheme to ease IP evaluation process between IP vendors and users. Complex system-on-a-chip design requires more and more IP modules from 3rd party vendors. What can be disclosed by the vendor without ...