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Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or ...

In order to overcome the problems of low detection rate of strong magnetic field interference, low signal-to-noise ratio and long control time of digital circuit signal transmission noise in traditional control methods, a noise control method of digital ...

In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, ...

This paper presents a MOOC-ready online FPGA laboratory platform which targets computer system experiments. Goal of design is to provide user with highly approximate experience and results as offline experiments. Rich functions are implemented by ...

Cartesian genetic programming (CGP) is a branch of genetic programming in which candidate designs are represented using directed acyclic graphs. Evolutionary circuit design is the most typical application of CGP. This paper presents a new software tool--...

The target-independent Virtual-FPGA (V-FPGA) is a virtual very-large-scale integration system architecture used to facilitate computer hardware evolution. It resides as a second configuration-layer on top of any hardware FPGA layer. The V-FPGA ...

Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP)...

The performance of any system strongly depends on effective design methods applied on various segments of that system. To provide an intelligent and smart architecture of a computer system, a dedicated design is needed which is both power friendly and ...

Three nonlinear reduced-order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal-oxide-semiconductor technologies where variability of the electrical characteristics of a transistor ...

The stepwise formal development of safety critical software is now a well established engineering practice, noticeably in railway systems. However, it has not been applied as successfully to hardware development, where formal methods are mainly used for ...

Since the early 1990's researchers have begun to apply evolutionary algorithms to design electronic circuits. Nowadays it is evident that the evolutionary design approach can automatically create efficient electronic circuits in many domains. This ...

In most of existing approaches, the reorganization of test vector sequence and reordering scan chains registers to reduce power consumption are solved separately, they are seen as independent procedures. In the paper it is shown that a correlation ...

With the development of VLSI，circuit Design for Testability has become the focus of attention. Fault diagnosis and detection VLSI has become an important part of the development of essential. This paper is based on DFT theory as background, introduced ...

Modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. Unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance ...

A novel multi-objective evolutionary mechanism for digital circuits is proposed. Firstly, each CLB of FPGA is configured as minimum evolutionary structure cell (MESC). The two-dimensional array consisted of MESCs by integer scale values is coded. And ...

An issue that arises in evolvable hardware is how to verify the correctness of the evolved circuit, especially in online evolution. The traditional exhaustive evaluation approach has made evolvable hardware unpractical to real-world applications. In ...

This paper proposes two bounded arithmetic operations, which are easily realized with current signals. Based on these two operations, a bounded algebra system suitable for describing current-mode digital circuits is developed and its relationship ...

A waveform polynomial for a digital circuit integrates both logic and timing information. It is applicable to design verification and test. This paper introduces a compact and manageable form, BPBDD, to represent and manipulate Boolean process based on ...

In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related ...

STAFAN (statistical fault analysis) is a well known testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over ...