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- research-articleNovember 2023
Buffer Times Between Scheduled Events in Resource Assignment Problem: A Conflict-Robust Perspective
Manufacturing & Service Operations Management (INFORMS-MSOM), Volume 25, Issue 6Pages 2268–2276https://doi.org/10.1287/msom.2022.0572Problem definition: In many resource scheduling problems for services with scheduled starting and completion times (e.g., airport gate assignment), a common approach is to maintain appropriate buffer between successive services assigned to a common ...
- ArticleApril 2005
Accounting for the skin effect during repeater insertion
GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSIPages 32–37https://doi.org/10.1145/1057661.1057671Since the skin effect will increase the propagation delay in an interconnect, it will also affect how to optimally select the number and size of the buffers. Failing to include the skin effect during buffer design may result in as much as 35% extra ...
- ArticleAugust 2003
Energy optimization techniques in cluster interconnects
ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and designPages 459–464https://doi.org/10.1145/871506.871620Designing energy-efficient clusters has recently become an important concern to make these systems economically attractive for many applications. Since the links and switch buffers consume the major portion of the power budget of the cluster, the focus ...
- ArticleOctober 1997
Critical voltage transition logic: an ultrafast CMOS logic family
The authors present a new kind of CMOS logic circuit that has a different structure and different operation mechanism compared to the existing logic circuits. Its unique delay propagation characteristic makes it much faster than the conventional CMOS ...
- ArticleMarch 1997
Internal power modelling and minimization in CMOS inverters
We present in this paper an alternative for the internal (short-circuit and overshoot) power dissipation estimation of CMOS structures. Using a first order macro-modelling, we consider submicronic additional effects such as: input slow dependency of ...
- ArticleMarch 1996
Design and selection of buffers for minimum power-delay product
Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed ...
- research-articleJune 1970
Buffer Behavior for Poisson Arrivals and Multiple Synchronous Constant Outputs
IEEE Transactions on Computers (ITCO), Volume 19, Issue 6Pages 530–534https://doi.org/10.1109/T-C.1970.222970A queuing model with a limited waiting room (buffer), Poisson arrivals, multiple synchronous servers (synchronous transmission channels), and constant services is studied. Using traffic intensity and number of transmission lines as parameters, the ...