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- research-articleSeptember 2013
CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded SystemsArticle No.: 9, Pages 1–10Clustered architectures have been proposed as a solution to the scalability problem of wide ILP processors. VLIW architectures, being wide-issue by design, benefit significantly from clustering. Such architectures, being both statically scheduled and ...
- research-articleOctober 2018
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsPages 45–54https://doi.org/10.1145/2465554.2465565Clustered VLIW architectures are statically scheduled wide-issue architectures that combine the advantages of wide-issue processors along with the power and frequency scalability of clustered designs. Being statically scheduled, they require that the ...
- research-articleJune 2013
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsPages 45–54https://doi.org/10.1145/2491899.2465565Clustered VLIW architectures are statically scheduled wide-issue architectures that combine the advantages of wide-issue processors along with the power and frequency scalability of clustered designs. Being statically scheduled, they require that the ...
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ACM SIGPLAN Notices: Volume 48 Issue 5 - ArticleMay 2012
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files
IPDPSW '12: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD ForumPages 462–469https://doi.org/10.1109/IPDPSW.2012.60Reconfigurable tile-based architectures can dynamically interconnect several tiles in order to establish processor instances with varying resource, performance, and energy characteristics at run time. These flexible processor instances offer a new ...
- ArticleOctober 2003
A scalable wide-issue clustered VLIW with a reconfigurable interconnect
CASES '03: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systemsPages 148–158https://doi.org/10.1145/951710.951731Clustered VLIW architectures have been widely adopted in modern embedded multimedia applications for their ability to exploit high degrees of ILP with reasonable trade-off in complexity and silicon costs. Studies have however shown limited performance ...