Export Citations
Save this search
Please login to be able to save your searches and receive alerts for new content matching your search criteria.
- research-articleFebruary 2014
Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture
ODES '14: Proceedings of the 11th Workshop on Optimizations for DSP and Embedded SystemsPages 25–32https://doi.org/10.1145/2568326.2568327For the exploitation of the available parallelism clustered Very Long Instruction Word (VLIW) processors rely on highly optimizing compilers. Aiming this parallelism, many advanced compiler concepts have been developed and proposed in the past. Many of ...
- research-articleSeptember 2013
CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded SystemsArticle No.: 9, Pages 1–10Clustered architectures have been proposed as a solution to the scalability problem of wide ILP processors. VLIW architectures, being wide-issue by design, benefit significantly from clustering. Such architectures, being both statically scheduled and ...
- research-articleOctober 2018
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsPages 45–54https://doi.org/10.1145/2465554.2465565Clustered VLIW architectures are statically scheduled wide-issue architectures that combine the advantages of wide-issue processors along with the power and frequency scalability of clustered designs. Being statically scheduled, they require that the ...
- research-articleJune 2013
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsPages 45–54https://doi.org/10.1145/2491899.2465565Clustered VLIW architectures are statically scheduled wide-issue architectures that combine the advantages of wide-issue processors along with the power and frequency scalability of clustered designs. Being statically scheduled, they require that the ...
Also Published in:
ACM SIGPLAN Notices: Volume 48 Issue 5 - research-articleJune 2012
WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture
LCTES '12: Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded SystemsPages 31–40https://doi.org/10.1145/2248418.2248424Worst-Case Execution Time (WCET) is one of the most important metrics in real-time embedded system design. For embedded systems with clustered VLIW architecture, register allocation, instruction scheduling, and cluster assignment are three key ...
Also Published in:
ACM SIGPLAN Notices: Volume 47 Issue 5 - articleJune 2007
Inter-cluster communication in VLIW architectures
ACM Transactions on Architecture and Code Optimization (TACO), Volume 4, Issue 2Pages 11–eshttps://doi.org/10.1145/1250727.1250731The traditional VLIW (very long instruction word) architecture with a single register file does not scale up well to address growing performance demands on embedded media processors. However, splitting a VLIW processor in smaller clusters, which are ...
- ArticleOctober 2003
Cluster assignment of global values for clustered VLIW processors
CASES '03: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systemsPages 32–40https://doi.org/10.1145/951710.951717In this paper high-level language (HLL) variables that are alive in a whole HLL function, across multiple scheduling units, are termed as global values. Due to their long live ranges and, hence, large impact on the schedule, the global values require ...
- ArticleJune 2002
Affinity-based cluster assignment for unrolled loops
ICS '02: Proceedings of the 16th international conference on SupercomputingPages 107–116https://doi.org/10.1145/514191.514209To compete performance-wise, modern VLIW processors must have fast clock rates and high instruction-level parallelism (ILP). Partitioning resources (functional units and registers) into clusters allows the processor to be clocked faster, but operand ...
- ArticleSeptember 2001
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors
PACT '01: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation TechniquesPages 175–184Abstract: This work presents a modulo scheduling framework for clustered ILP processors that integrates the cluster assignment, instruction scheduling and register allocation steps in a single phase. This unified approach is more effective than ...