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Olfactory experience has great advantages in awakening human memories and emotions, which may even surpass vision in some cases. Studies have proved that olfactory scene descriptions in images and text content can also arouse human olfactory imagination,...

 Recognizing facial expressions rely on facial parts’ movement (action units) such as eyes, mouth, and nose. Existing methods utilize complex subnetworks to learn part-based facial features or train neural networks with an extensively perturbed dataset. ...

We introduce a software package integrated with the molecular dynamics software LAMMPS for fluctuating hydrodynamics simulations of fluid-structure interactions subject to thermal fluctuations. The package is motivated to provide dynamic thermostats to ...

Coarse-grained reconfigurable architecture (CGRA) can provide strong capability of parallel computation and flexibility; it is becoming a promising platform for mobile computing. As mobile platforms increasingly demand power, more and more mobile ...

Molecular Dynamics method(MD) has been used for simulations of the structure and dynamics of soft matter, biological molecules, fluid and more. However, the calculation cost has been a major bottleneck. Coarse-grained molecular dynamics is one of the ...

This paper proposes a working framework for SAR data parallel processing using computing cluster, which includes a master node and a number of computing nodes. This framework supports coarse-grained data processing and the master node controls the whole ...

Triple modular redundancy (TMR) is a common method to implement fault-tolerant circuits. Traditionally, TMR is realized by triplication of components. In order to reduce the area overhead of TMR another approach was proposed on coarse grained ...

Hardware redundancy is a common method for improving the reliability of a system. The disadvantage of this approach is the hardware overhead and the additional power consumption. This contribution proposes a strategy for implementing low-cost triple ...

In this contribution we apply a novel strategy for partial remapping to significantly enhance the reliability of coarse-grained reconfigurable architectures. If a component of the architecture is affected by a permanent error, it will be deactivated and ...

Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable ...

This study compares the speed, area, and latency of shift-and-add arithmetic implemented within fine-grained FPGA resources and within a proposed coarse-grained embedded block for FPGAs. It begins by optimizing the mapping of various shift-and-add ...

With the increasing power density of deep submicron technology, temperature becomes one of the dominating factors for the reliability of integrated circuits. Coarse-grained reconfigurable devices typically exhibit spatially nonuniform activity, which ...

To achieve low-cost low-power high-performance embedded image/video processing and analysis, in this paper, a coarse-grained reconfigurable image stream processor (CRISP) architecture is proposed. With the reconfigurable datapath and interconnection ...

Multi-context reconfigurable arrays provide the ability for fast dynamic reconfiguration once the configurations have been stored into the architecture's context memory. Besides switching the context of the entire array it is also possible to ...

DSP architectures often feature multiple register files with sparse connections to a large set of ALUs. For such DSPs, traditional register allocation algorithms suffer from a lot of problems, including a lack of retargetability and phase-ordering ...

The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. ...

In this paper, we present a synthesis technique targeted toward coarse-grained antifuse-based field- programmable gate arrays (FPGAs). A macrologic cell, in this class of FPGAs, has multiple inputs and multiple outputs. A library of small logic cells ...