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- research-articleNovember 2024
Efficient deployment of Single Shot Multibox Detector network on FPGAs
AbstractFPGAs, characterized by their low power consumption and swift response, are ideally suited for parallel computations associated with object detection tasks, making them a popular choice for target detection and neural network acceleration. ...
Highlights- Parallel computation boosts speed and efficiency in convolutional layers.
- Integrated parallel processing enhances convolution activation pooling.
- Efficient memory management reduces read/write time for feature layers.
- ...
- research-articleAugust 2023
Secure Video Streaming Using Dedicated Hardware
Journal of Signal Processing Systems (JSPS), Volume 95, Issue 10Pages 1265–1275https://doi.org/10.1007/s11265-023-01886-4AbstractThe purpose of this article is to present a system that enhances the security, efficiency, and reconfigurability of an Internet-of-Things (IoT) system used for surveillance and monitoring. A Multi-Processor System-On-Chip (MPSoC) composed of ...
- research-articleJune 2022
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
HEART '22: Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable TechnologiesPages 33–41https://doi.org/10.1145/3535044.3535049The novel communication 6G requires raw data rates of up to 400 Gbit s− 1 in a single Field Programmable Gate Array (FPGA) front-end. For these high data rates, a Software Defined Radio (SDR) on a multi-core processor reaches a performance limit due to ...
- research-articleNovember 2021
A scalable and efficient convolutional neural network accelerator using HLS for a system-on-chip design
Microprocessors & Microsystems (MSYS), Volume 87, Issue Chttps://doi.org/10.1016/j.micpro.2021.104363AbstractThis paper presents a configurable convolutional neural network accelerator (CNNA) for a system-on-chip (SoC). The goal was to accelerate inference in different deep learning networks on an embedded SoC platform. The presented CNNA has ...
Highlights- A scalable CNN architecture with a single computation engine for FPGA acceleration.
- research-articleDecember 2021
Design of Picture Classification System Based on Embedded PYNQ Architecture
EITCE '21: Proceedings of the 2021 5th International Conference on Electronic Information Technology and Computer EngineeringPages 420–424https://doi.org/10.1145/3501409.3501486With the rapid development of deep learning, traditional convolutional neural networks have achieved success in various fields. In order to meet the situation that FPGAs and other devices have less available resources, a picture classification system ...
- research-articleFebruary 2021
Design and implementation of YOLOv3-Tiny accelerator based on PYNQ-Z2 heterogeneous platform
EITCE '20: Proceedings of the 2020 4th International Conference on Electronic Information Technology and Computer EngineeringPages 1097–1102https://doi.org/10.1145/3443467.3443911Convolutional Neural Network (CNN) has been widely used in computer vision fields such as image recognition and target detection. However, in the forward reasoning stage, many practical applications often require features of low latency and low power ...
- research-articleJuly 2020
Enabling transparent hardware acceleration on Zynq SoC for scientific computing
- Luca Stornaiuolo,
- Filippo Carloni,
- Riccardo Pressiani,
- Giuseppe Natale,
- Marco Santambrogio,
- Donatella Sciuto
In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and overlays to ease the integration of functionalities of the programmable logic into ...
- research-articleJune 2020
BNNsplit: binarized neural networks for embedded distributed FPGA-based computing systems
In the past few years, Convolutional Neural Networks (CNNs) have seen a massive improvement, outperforming other visual recognition algorithms. Since they are playing an increasingly important role in fields such as face recognition, augmented reality or ...
- research-articleJanuary 2018
General-Purpose Computing with Soft GPUs on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 11, Issue 1Article No.: 5, Pages 1–22https://doi.org/10.1145/3173548Using field-programmable gate arrays (FPGAs) as a substrate to deploy soft graphics processing units (GPUs) would enable offering the FPGA compute power in a very flexible GPU-like tool flow. Application-specific adaptations like selective hardening of ...