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In this paper, we present a broadband low-noise amplifier (LNA), using active-feedforward noise-cancellation and complementary n/pMOS configurations. Based on traditional common-gate (CG) and common-source (CS) noise canceling topology, the ...

In this manuscript, a low noise amplifier (LNA) circuit with low power consumption of 5.3 mW for 3–12 GHz ultra-wideband (UWB) is designed in 90 nm standard CMOS process. A noise-canceling (NC) approach consisting of both common-gate (CG) and ...

• A low noise amplifier circuit with low power consumption of 5.3 mW, operated with 0.7 V V dd for 3–12 GHz is designed in 90 nm standard CMOS process. This LNA achieves noise-figure (NF) of 2.28–4.0 dB.
• Noise-canceling approach ...

In this paper, Variable Gain LNA (VG-LNA) parameters are optimized using the Particle Swarm Optimization (PSO), Firefly Algorithm (FA), and Genetic Algorithm (GA). A comparison of the three optimization techniques has been done and FA is ...

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• VG-LNA parameters optimized using PSO, FA and GA.
• A comparison of the three optimization techniques has been done and FA is depicting better results over GA and PSO.
• VG-LNA is composed of a Complementary Common Gate (CCG) and ...

A 0.5–3.0 GHz passive mixer based receiver front-end (RFE) is presented. This RFE consists of low noise amplifier, passive mixer, transimpedance amplifier (TIA) and local oscillator signal generator. In order to reduce the power ...

In this paper, a low-noise amplifier operating in K-band is designed based on a 65nm CMOS process. The key parameters of a low-noise amplifier are noise figure and gain. The design takes a two-stage differential common source structure, and the input ...

Using TSMC RF CMOS 65nm process design a K band two-stage low-noise amplifier(LNA) chip, the working frequency band is 18∼20GHz, the chip is used in wireless communication receivers, the chip area of 570μm× 988μm, using 1V power supply. The first stage ...

A new transformer matching method for ultra-wideband (UWB) low noise amplifier is presented, which effectively extends the bandwidth and has little effect on the circuit noise. Low-frequency gain compression are realized by combining Frlan-style ...

• The proposed LNA is implemented to achieve outstanding overall performance in bandwidth, NF, linearity and circuit area.
• A new idea for ultra-wideband low-noise amplifiers based on the transformer matching method is presented.
• The ...

In this work, we report a single-voltage-supply-operated current-reused complementary 3.7–11.9 GHz CMOS low-noise amplifier (LNA) for sub-6 GHz 5G systems. The body-floating and self-forward-bias technique, i.e., the body of the transistor is ...$\mathrm{}$

In this study, a low-noise amplifier is quantum-mechanically analyzed to study the behavior of the noise figure. The analysis view has been changed from classic to quantum, because using quantum theory produces some degrees of freedom, ...

In this paper, a thorough co-design procedure for the integrated PIN-diode limiter and low noise amplifier (LNA) is presented. A 27 GHz–35 GHz wideband integrated limiter low noise amplifier (limiter-LNA) is fabricated with the ...

Design-technology co-optimization (DTCO) for the low noise amplifier (LNA) in quantum computing peripheral circuit is explored. Using the 22 nm fully-depleted‑silicon-on- insulator (FDSOI) transistor model that was calibrated at 4 K, ...

Modern time microwave stages require low power consumption, low size, low-noise amplifier (LNA) designs with high-performance measures. These demands need a single transistor LNA design, which is a challenging multi-objective, multi-dimensional ...

In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. ...

• Designing a LNA using modified current reuse structure, feedforward structure and self forward body bias.

An ultra-wideband (12–18 GHz) low-noise amplifier (LNA) using a 65 nm CMOS technology is proposed, in which a common-source cascode structure with capacitive feedback technique is employed, leading to the excellent gain flatness. In order to ...

In this paper, a CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented. The proposed CMOS LNA is designed using common-gate (CG) topology at the first stage to achieve ultra wideband input matching. The common-...

This paper presents a wideband low power balun LNA with double noise canceling techniques and symmetric outputs. First, the CS amplifier in parallel with the CG stage cancels the noise and distortion of the CG amplifier. Second, an auxiliary ...

An efficient architecture to design low noise amplifier methods aimed at reducing the radar cross-section (RCS) under the X - and Y-polarizations with incident waves, the characteristics of radiation has been analyzed. The goal is to carry out ...

This article deals the design and analysis of CMOS RF receiver front-end with the optimization of single-stage and two-stage low noise amplifier (LNA) for wireless applications. The low noise, high gain and better linearity for 3–10 GHz ultra ...

In literature double recycling folded cascode operational transconductance amplifier (DRFC-OTA) is realized to achieve higher transconductance. To realize preamplifier for bio-medical applications, it is necessary to design an OTA with lower ...${}_{}{}_{}$$\mathrm{}\mathrm{}{}_{\mathit{}}$$\mathrm{}\mathrm{}\mathrm{}$${}_{\mathit{}}$$\mathrm{}{\mathrm{}}^{\mathrm{}}$

This paper presents a wideband blocker-tolerant direct $\Delta \Sigma$ receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker ...$\mathrm{}$