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- research-articleMarch 2023
A first polynomial non-clausal class in many-valued logic
Fuzzy Sets and Systems (FSTS), Volume 456, Issue CPages 1–37https://doi.org/10.1016/j.fss.2022.10.008AbstractThe relevance of polynomial classes of formulas to deductive efficiency motivated their further research, and currently, a great number of such classes is known. Nevertheless, they have been exclusively sought in the setting of ...
- research-articleJuly 2022
- research-articleOctober 2021
Improved algorithms for the general exact satisfiability problem
Theoretical Computer Science (TCSC), Volume 889, Issue CPages 60–84https://doi.org/10.1016/j.tcs.2021.07.036AbstractThe Exact Satisfiability problem asks if we can find a satisfying assignment to each clause such that exactly one literal in each clause is assigned 1, while the rest are all assigned 0. We can generalise this problem further by ...
- research-articleMarch 2020
Grid based clustering for satisfiability solving
AbstractThe originality of this work resides into the exploitation of data mining techniques for problem solving. Two major phases define this work. The first one is to determine the clustering technique that best suits each SAT instance based ...
Highlights- Study of instances distribution to deduce the most appropriate clustering technique.
- research-articleFebruary 2019
High Performance Reversible Direct Data Synthesizer for Radio Frequency Applications
Mobile Networks and Applications (MNET), Volume 24, Issue 1Pages 224–233https://doi.org/10.1007/s11036-018-1200-2AbstractDesign of Reversible logic gate enabled Reconfigurable Direct digital synthesizer is evaluated here. The need for Direct Digital Synthesizers (DDS) inherently finds application in the area of radio frequency communication. DDS is a method of ...
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- articleJune 2018
A Verified SAT Solver Framework with Learn, Forget, Restart, and Incrementality
Journal of Automated Reasoning (JAUR), Volume 61, Issue 1-4Pages 333–365https://doi.org/10.1007/s10817-018-9455-7We developed a formal framework for conflict-driven clause learning (CDCL) using the Isabelle/HOL proof assistant. Through a chain of refinements, an abstract CDCL calculus is connected first to a more concrete calculus, then to a SAT solver expressed ...
- articleNovember 2016
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 89, Issue 2Pages 337–345https://doi.org/10.1007/s10470-016-0786-1A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, ...
- research-articleNovember 2015
Theory propagation and reification
Science of Computer Programming (SCPR), Volume 111, Issue P1Pages 3–22https://doi.org/10.1016/j.scico.2014.05.013SAT Modulo Theories (SMT) is the problem of determining the satisfiability of a formula in which constraints, drawn from a given constraint theory T, are composed with logical connectives. The DPLL(T) approach to SMT has risen to prominence as a ...
- articleFebruary 2014
Lower Bound on Average-Case Complexity of Inversion of Goldreich's Function by Drunken Backtracking Algorithms
Theory of Computing Systems (TOCSYS), Volume 54, Issue 2Pages 261–276https://doi.org/10.1007/s00224-013-9514-8We prove an exponential lower bound on the average time of inverting Goldreich's function by drunken backtracking algorithms; this resolves the open question stated in Cook et al. (Proceedings of TCC, pp. 521---538, 2009 ). The Goldreich's function ...
- ArticleApril 2013
A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and Simulations
ITNG '13: Proceedings of the 2013 10th International Conference on Information Technology: New GenerationsPages 217–222https://doi.org/10.1109/ITNG.2013.36A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled using Verilog-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm leading ...
- articleSeptember 2012
Extracting a DPLL Algorithm
Electronic Notes in Theoretical Computer Science (ENTCS) (ENTCS), Volume 286Pages 243–256https://doi.org/10.1016/j.entcs.2012.08.016We formalize a completeness proof for the DPLL proof system and extract a DPLL SAT solver from it. When applied to a propositional formula in conjunctive normal form the program produces either a satisfying assignment or a DPLL derivation which shows ...
- ArticleApril 2012
A Novel SAR Fast-Locking Digital PLL: SPICE Modeling and Simulations
ITNG '12: Proceedings of the 2012 Ninth International Conference on Information Technology - New GenerationsPages 472–477https://doi.org/10.1109/ITNG.2012.108A novel fast-locking DPLL based on the Successive-Approximation Register (SAR) is presented and modeled using SPICE. The DPLL has two distinct stages of operation: 1) A coarse-tuning stage which employs frequency tracking to bring the VCO and reference ...
- articleMarch 2012
Exact thresholds for DPLL on random XOR-SAT and NP-complete extensions of XOR-SAT
This paper discusses a model of constraint satisfaction problems known as uniquely extendible constraint satisfaction problems. This model includes and generalizes XOR-SAT, and the model includes an NP-complete problem that appears to share many of the ...
- posterMay 2011
A new low power and area efficient semi-digital PLL architecture for low bandwidth applications
GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSIPages 363–366https://doi.org/10.1145/1973009.1973083Traditional PLL architecture uses one control voltage for both integrated and proportional part of the oscillator. Digital PLL architecture uses 2 control words for integrated and proportional part of the oscillator. In this paper, we describe a new ...
- ArticleApril 2011
A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations
ITNG '11: Proceedings of the 2011 Eighth International Conference on Information Technology: New GenerationsPages 777–784https://doi.org/10.1109/ITNG.2011.136A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed ...
- articleFebruary 2011
On the power of clause-learning SAT solvers as resolution engines
Artificial Intelligence (ARTI), Volume 175, Issue 2Pages 512–525https://doi.org/10.1016/j.artint.2010.10.002In this work, we improve on existing results on the relationship between proof systems obtained from conflict-driven clause-learning SAT solvers and general resolution. Previous contributions such as those by Beame et al. (2004), Hertel et al. (2008), ...
- ArticleNovember 2010
Implementation of Coordinate Rotation Algorithm for Digital Phase Locked Loop System in In-Phase and Quadrature Channel Signal Processing
ICETET '10: Proceedings of the 2010 3rd International Conference on Emerging Trends in Engineering and TechnologyPages 721–725https://doi.org/10.1109/ICETET.2010.164Digital Signal Processing (DSP) system involves a wide spectrum of DSP algorithms for its realization and is often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal ...
- ArticleOctober 2010
Research on Digital Phase-Locked Loop about K/Ka-Band High Precision Receiver
ISDEA '10: Proceedings of the 2010 International Conference on Intelligent System Design and Engineering Application - Volume 02Pages 185–188https://doi.org/10.1109/ISDEA.2010.171A dual one-way ranging system (DOWR) can provide very high precision ranging between two carrier phase transceiver-receiver systems. In microwave ranging system, the accuracy of inter-satellite ranging is mainly limited by the stability of the ...
- research-articleAugust 2010
Making deduction more effective in SAT solvers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 29, Issue 8Pages 1271–1284https://doi.org/10.1109/TCAD.2010.2049135Satisfiability (SAT) solvers often benefit from transformations of the formula to be decided that allow them to do more through deduction and decrease their reliance on enumeration. For formulae in conjunctive normal form, subsumed clauses may be ...
- ArticleJuly 2010
A non-prenex, non-clausal QBF solver with game-state learning
SAT'10: Proceedings of the 13th international conference on Theory and Applications of Satisfiability TestingPages 128–142https://doi.org/10.1007/978-3-642-14186-7_12We describe a DPLL-based solver for the problem of quantified boolean formulas (QBF) in non-prenex, non-CNF form. We make two contributions. First, we reformulate clause/cube learning, extending it to non-prenex instances. We call the resulting technique ...