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Testing the RF functions of systems-on-chip incurs a very high cost. Built-in test is a promising alternative to facilitate testing and reduce cost. However, designing built-in test circuits that tap into the sensitive RF signal paths, in order to ...

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources ...

This paper develops a technique, using a built-in detector, for measuring the specifications of RF subsystems and fine-tuning them with a feedback control algorithm. At the same time, optimum power consumption points can be chosen from different biasing ...

This paper describes the theory and chip measurements of a built-in test technique for RF receivers which uses simple RF amplitude detectors. The method has been used to measure the performance parameters of a 940 MHz RF receiver front-end with a mixer ...

Today component- and service-based technologies play a central role in many aspects of enterprise computing. However, although the technologies used to define, implement, and assemble components have improved significantly over recent years, ...

This article describes a set of on-chip testing techniques and their application to integrated wireless RF transceivers. The objective is to reduce final product cost and accelerate time to market by providing means of testing the entire transceiver ...

A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of time compression schemes with respect to errors detected are developed. The use of two or more of these methods together is ...

A new test data reduction technique called accumulator compression testng (ACT) is proposed. ACT is an extension of syndrome testing. It is shown that the enumeration of errors missed by ACT for a unit under test is equivalent to the number of ...

A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible.

A hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a ...