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A Tile-based Interconnect Model for FPGA Architecture Exploration

Authors:

Jinmei LaiAuthors Info & Claims

GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI

Pages 113 - 118

https://doi.org/10.1145/3386263.3406927

Published: 07 September 2020 Publication History

Abstract

Modern FPGA has complex interconnect, like curve wires and two-level local muxs (global wires -> block input pins). Existing interconnect model (CB-SB) cannot describe these routing fabrics, hindering CAD exploration of modern FPGA.

This paper presents INTB (Interconnect block) model to solve this problem. To represent all routing resources including curve wires and two-level local muxs, a five-side INTB is defined at each FPGA tile. Meanwhile, for simple description of large architecture space, hierarchical model parameters are designed. Besides, we modify CAD flow to apply INTB model: a memory-efficient method based on tile is adopted to generate routing resource graph (RRG); New strategies of routing cost estimation are used to route short and curve wires.

INTB model and CAD modifications are implemented in VTR 8.0. The experiments include two parts: first, it is verified that our model is accurate and compatible with CB-SB model. The results show difference of switch area and timing between these two models is 1.21% and 1.11%. Second, our model is used to explore modern FPGA interconnect. Compared to original routing fabrics of VTR, curve wires reduce critical path delay by 11.77% and two-level local muxs reduce channel width by 17.36%.

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References

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Petelin, Oleg, and Vaughn Betz. "The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer." 2016 26th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2016.

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David Lewis et al. Architectural Enhancements in Stratix V. In FPGA, pages 147--156, 2013.

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Lemieux, Guy, et al. "Directional and single-driver wires in FPGA interconnect." Proceedings. 2004 IEEE International Conference on Field-Programmable Technology (IEEE Cat. No. 04EX921). IEEE, 2004.

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Hutton, Michael D., Bruce B. Pedersen, and II James G. Schleicher. "Dedicated resource interconnects." U.S. Patent No. 7,368,942. 6 May 2008.

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E. Hung, "Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, 2015, pp. 1--4.

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Young, Steven P. "Integrated circuit with programmable routing structure including straight and diagonal interconnect lines." U.S. Patent No. 7,279,929. 9 Oct. 2007.

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Wang, Zhen, Ding Xie, and Jinmei Lai. "FPGA interconnect architecture exploration based on a statistical model." 2011 21st International Conference on Field Programmable Logic and Applications. IEEE, 2011.

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VTR: https://github.com/verilog-to-routing/vtr-verilog-to-routing

Cited By

Liu YXiong WWang JLai J(2024)A new model for parametrically evaluating the routability of GRM FPGAIEICE Electronics Express10.1587/elex.20.2023055621:3(20230556-20230556)Online publication date: 10-Feb-2024
https://doi.org/10.1587/elex.20.20230556
Shi KWang L(2024)An Open-Source Tool to Model and Explore Complex Routing Architecture for FPGA2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617494(734-739)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617494
Shi KZhou XZhou HWang L(2022)An Optimized GIB Routing Architecture with Bent Wires for FPGAACM Transactions on Reconfigurable Technology and Systems10.1145/351959916:1(1-28)Online publication date: 5-Mar-2022
https://dl.acm.org/doi/10.1145/3519599
Show More Cited By

Index Terms

A Tile-based Interconnect Model for FPGA Architecture Exploration
1. Hardware
  1. Electronic design automation
    1. Modeling and parameter extraction
    2. Physical design (EDA)
      1. Wire routing
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Programmable interconnect

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cover image ACM Other conferences

GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI

September 2020

597 pages

ISBN:9781450379441

DOI:10.1145/3386263

General Chairs:
Tinoosh Mohsenin
University of Maryland, Baltimore County, USA
,
Weisheng Zhao
Beihang University, China
,
Program Chairs:
Yiran Chen
Duke University, USA
,
Onur Mutlu
ETH Zurich, Switzerland

Copyright © 2020 ACM.

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New York, NY, United States

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Published: 07 September 2020

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GLSVLSI '20

GLSVLSI '20: Great Lakes Symposium on VLSI 2020

September 7 - 9, 2020

Virtual Event, China

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Liu YXiong WWang JLai J(2024)A new model for parametrically evaluating the routability of GRM FPGAIEICE Electronics Express10.1587/elex.20.2023055621:3(20230556-20230556)Online publication date: 10-Feb-2024
https://doi.org/10.1587/elex.20.20230556
Shi KWang L(2024)An Open-Source Tool to Model and Explore Complex Routing Architecture for FPGA2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617494(734-739)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617494
Shi KZhou XZhou HWang L(2022)An Optimized GIB Routing Architecture with Bent Wires for FPGAACM Transactions on Reconfigurable Technology and Systems10.1145/351959916:1(1-28)Online publication date: 5-Mar-2022
https://dl.acm.org/doi/10.1145/3519599
Zheng SQian JZhou HWang L(2022)GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00050(282-286)Online publication date: Aug-2022
https://doi.org/10.1109/FPL57034.2022.00050
Qian JShen YShi KZhou HWang L(2021)General routing architecture modelling and exploration for modern FPGAs2021 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT52863.2021.9609935(1-9)Online publication date: 6-Dec-2021
https://doi.org/10.1109/ICFPT52863.2021.9609935

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