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Integrating register allocation and instruction scheduling for RISCs

Authors:

David G. Bradlee,

Susan J. Eggers,

Robert R. HenryAuthors Info & Claims

ACM SIGPLAN Notices, Volume 26, Issue 4

Pages 122 - 131

https://doi.org/10.1145/106973.106986

Published: 01 April 1991 Publication History

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Cited By

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(2023)BibliographyEngineering a Compiler10.1016/B978-0-12-815412-0.00023-1(793-813)Online publication date: 2023
https://doi.org/10.1016/B978-0-12-815412-0.00023-1
Cooper KTorczon L(2023)Scalar OptimizationEngineering a Compiler10.1016/B978-0-12-815412-0.00016-4(517-573)Online publication date: 2023
https://doi.org/10.1016/B978-0-12-815412-0.00016-4
(2012)BibliographyEngineering a Compiler10.1016/B978-0-12-088478-0.00024-4(765-785)Online publication date: 2012
https://doi.org/10.1016/B978-0-12-088478-0.00024-4
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Index Terms

Integrating register allocation and instruction scheduling for RISCs
1. Computer systems organization
  1. Architectures
    1. Other architectures
    2. Serial architectures
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Scheduling

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The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. ...

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Information

Published In

ACM SIGPLAN Notices Volume 26, Issue 4

Special issue of a journal and a proceedings

Apr. 1991

305 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/106973

Editor:
David A. Patterson
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
April 1991
320 pages
ISBN:0897913809
DOI:10.1145/106972
Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 01 April 1991

Published in SIGPLAN Volume 26, Issue 4

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(2023)BibliographyEngineering a Compiler10.1016/B978-0-12-815412-0.00023-1(793-813)Online publication date: 2023
Cooper KTorczon L(2023)Scalar OptimizationEngineering a Compiler10.1016/B978-0-12-815412-0.00016-4(517-573)Online publication date: 2023
(2012)BibliographyEngineering a Compiler10.1016/B978-0-12-088478-0.00024-4(765-785)Online publication date: 2012
Govindarajan R(2009)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420043839.ch19(19-1-19-57)Online publication date: 7-Dec-2009
Cutcutache IWong W(2007)Fast, frequency‐based, integrated register allocation and instruction schedulingSoftware: Practice and Experience10.1002/spe.86038:11(1105-1126)Online publication date: 6-Nov-2007
Cooper KTorczon L(2003)Engineering a CompilerundefinedOnline publication date: 11-Dec-2003
Touati S(2001)Register Saturation in Superscalar and VLIW CodesCompiler Construction10.1007/3-540-45306-7_15(213-228)Online publication date: 23-Mar-2001
Lozano RSchulte C(2019)Survey on Combinatorial Register Allocation and Instruction SchedulingACM Computing Surveys10.1145/320092052:3(1-50)Online publication date: 18-Jun-2019
Tran KCarlson TKoukos KSjalander MSpiliopoulos VKaxiras SJimborean A(2018)Static Instruction Scheduling for High Performance on Limited HardwareIEEE Transactions on Computers10.1109/TC.2017.276964167:4(513-527)Online publication date: 1-Apr-2018
Tran KCarlson TKoukos KSjälander MSpiliopoulos VKaxiras SJimborean AReddi VSmith ATang L(2017)Clairvoyance: look-ahead compile-time schedulingProceedings of the 2017 International Symposium on Code Generation and Optimization10.5555/3049832.3049852(171-184)Online publication date: 4-Feb-2017
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Fast, frequency-based, integrated register allocation and instruction scheduling

Cooperative register allocation and instruction scheduling

Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors

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