Article

A generic micro-architectural test plan approach for microprocessor verification

Authors:

Kirill ShoikhetAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 769 - 774

https://doi.org/10.1145/1065579.1065785

Published: 13 June 2005 Publication History

Get Access

Abstract

Modern microprocessors share several common types of micro-architectural building blocks. The rising complexity of the micro-architecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a design-independent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design.

References

[1]

A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test program generation for functional verification of PowerPC processors in IBM. In Proceedings of the 32nd Design Automation Conference, pages 279--285, June 1995.

Digital Library

Google Scholar

[2]

D. V. Campenhout, T. Mudge, and J. P. Hayes. High-level test generation for design verification of pipelined microprocessors. In Proceedings of the 36th Design Automation Conference, pages 185--188, June 1999.

Digital Library

Google Scholar

[3]

L. Fournier, Y. Arbetman, and M. Levinger. Functional verification methodology for microprocessors using the Genesys test-program generator. In Proceedings of the 1999 Design, Automation and Test in Europe Conference (DATE), pages 434--441, March 1999.

Digital Library

Google Scholar

[4]

H. Iwashita, S. Kowatari, T. Nakata, and F. Hirose. Automatic test program generation for pipelined processors. In Proceedings of the International Conference on Computer Aided Design, pages 580--583, November 1994.

Digital Library

Google Scholar

[5]

K. Kohno and N. Matsumoto. A new verification methodlogy for complex pipeline behavior. In Proceedings of the 38th Design Automation Conference, pages 816--821, 2001.

Digital Library

Google Scholar

[6]

S. Ur and Y. Yadin. Micro-architecture coverage directed generation of test programs. In Proceedings of the 36th Design Automation Conference, pages 175--180, June 1999.

Digital Library

Google Scholar

[7]

J.-T. Yen and Q. R. Yin. Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor. In Proceedings of the 37th Design Automation Conference, pages 718--723, June 2000.

Digital Library

Google Scholar

[8]

A. Adir, E Bin, O. Peled, and A. Ziv. A Test Program Generator for Micro-Architecture Flow Verification. In Proceedings of the HLDVT 2003, pagse 23--28.

Digital Library

Google Scholar

[9]

Adir, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M. and Ziv, A. Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. IEEE Design & Test of Computers, Mar-Apr. 2004, 84--93.

Digital Library

Google Scholar

[10]

A. Ziv. Cross-Product Functional Coverage Measurement with Temporal Properties-based Assertions. In Proceedings of the 2003 Design Automation and Test in Europe (DATE'03)

Digital Library

Google Scholar

[11]

R. Grinwald, E. Harel, M. Orgad, S. Ur and A. Ziv. User Defined Coverage - A Tool Supported Methodology for Design Verification. In Proceedings of the 35th Design Automation Conference 1998. pages 158--165

Digital Library

Google Scholar

[12]

M. Aharoni, S. Asaf, L Fournier, A. Koyfman and R. Nagel. FPgen A Deep-Knowledge Test Generator for Floating Point Verification, HLDVT 2003, pages 17--22

Google Scholar

[13]

C. May, E. Silha, R. Simpson and H. Warren. The PowerPC Architecture. In Morgan Kaufmann, 1994.

Google Scholar

[14]

Julia Dushina, Mike Benjamin, Daniel Geist. Semi-Formal Test Generation with Genevieve. DAC 2001.

Digital Library

Google Scholar

Cited By

View all

Barboza EKetkar MGratz PHu J(2024)Aiding Microprocessor Performance Validation with Machine Learning2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00011(1-9)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00011
Hazra AGhosh PDasgupta PChakrabarti P(2012)Cohesive Coverage ManagementJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5308-128:4(449-468)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1007/s10836-012-5308-1
Yang FHuang WHuang ILevitan S(2007)Automatic verification of external interrupt behaviors for microprocessor designProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278701(896-901)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278701
Show More Cited By

Index Terms

A generic micro-architectural test plan approach for microprocessor verification
1. Hardware
  1. Hardware validation
    1. Functional verification

Recommendations

Design-for-testability features and test implementation of a giga hertz general purpose microprocessor

This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved ...
Grammar-based fuzz testing for microprocessor RTL design
Abstract
Recently, agile hardware design (AHD) methodology has been proposed to alleviate the productivity crisis brought by the growing complexity of modern microprocessor design. One of the key techniques in AHD is the adoption of hardware ...
Highlights
- A method to combine fuzz testing and symbolic simulation for RTL verification.
- ...
Automation of Test Program Synthesis for Processor Post-silicon Validation

Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is difficult with any of the external testing techniques. Evolutionary approaches are used for the automatic synthesis of SBST programs. However, a number of hard-...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC05

Sponsor:

DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
341
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Barboza EKetkar MGratz PHu J(2024)Aiding Microprocessor Performance Validation with Machine Learning2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00011(1-9)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00011
Hazra AGhosh PDasgupta PChakrabarti P(2012)Cohesive Coverage ManagementJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5308-128:4(449-468)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1007/s10836-012-5308-1
Yang FHuang WHuang ILevitan S(2007)Automatic verification of external interrupt behaviors for microprocessor designProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278701(896-901)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278701
Gluska ASentovich E(2006)Practical methods in coverage-oriented verification of the merom microprocessorProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146996(332-337)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1146996
Azatchi HFournier LMarcus EUr SZiv AZohar K(2006)Advanced Analysis Techniques for Cross-Product CoverageIEEE Transactions on Computers10.1109/TC.2006.17355:11(1367-1379)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TC.2006.173

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Design-for-testability features and test implementation of a giga hertz general purpose microprocessor

Grammar-based fuzz testing for microprocessor RTL design

Automation of Test Program Synthesis for Processor Post-silicon Validation