Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers

Reviewer: Ned Chapin

The author considers two issues in this paper dealing with pipelined computers: data dependencies and precise interrupts. A companion issue, not focused on, is branch instructions. For all three issues, execution speed is the author's concern. In a multiprocessing pipelined computer, one process may have to wait for data from another process, slowing performance overall. Also, when virtual memory is used, interrupts must be precisely timed for the contents of storage to be as expected by the programmer. In this paper, the author proposes a hardware solution that improves computer performance by reducing the data dependencies and, at the same time, provides for precise interrupts. To support the proposal, the author reports simulations showing improvement exceeding 150 percent under some conditions. The author calls the proposal a register update unit (RUU), and places it after the decode and issue unit and before the functional units. The author says his proposal is based on a modification of Tomasulo's algorithm. He covers two cases in some detail—the RUU with bypass logic and with limited bypass logic. The RUU works like managing a queue. The head of the queue points to the instruction needed for a precise interrupt; the tail points to the next available slot for the use of the decode and issue unit. The most stimulating part of this paper is the author's willingness to address the interdependency of interrupts and data dependencies, which often are discussed as though they had scant interactions. The author's seemingly close tie to Cray hardware and his limited discussion of hardware alternatives, however, left me unconvinced about the possible value of his proposal for other hardware.