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A 60-GHz phased array receiver front-end in 0.13-µm CMOS technology

Authors:

Chao-Shiun Wang,

Juin-Wei Huang,

Chorng-Kuang WangAuthors Info & Claims

IEEE Transactions on Circuits and Systems Part I: Regular Papers, Volume 56, Issue 10

Pages 2341 - 2352

https://doi.org/10.1109/TCSI.2009.2031697

Published: 01 October 2009 Publication History

Abstract

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, a g_m-boosted current-reuse low-noise amplifier (LNA), a subharmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate downconversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-µm 1P8M RF CMOS technology, the chip occupies an active area of 1.1 × 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and --27 dBm, respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.

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Cited By

Zhou CZhang LWang YYu ZQian H(2014)A 4-bit CMOS phase shifter for millimeter-wave phased arraysAnalog Integrated Circuits and Signal Processing10.1007/s10470-014-0287-z79:3(461-468)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1007/s10470-014-0287-z
Tang TMurray ARoy S(2010)Methodology of statistical RTS noise analysis with charge-carrier trapping modelsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2010.204398857:5(1062-1070)Online publication date: 1-May-2010
https://dl.acm.org/doi/10.1109/TCSI.2010.2043988

A 60-GHz phased array receiver front-end in 0.13-µm CMOS technology
1. Hardware
  1. Electronic design automation
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image IEEE Transactions on Circuits and Systems Part I: Regular Papers

IEEE Transactions on Circuits and Systems Part I: Regular Papers Volume 56, Issue 10

October 2009

227 pages

ISSN:1549-8328

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IEEE Press

Publication History

Published: 01 October 2009

Revised: 21 June 2009

Received: 23 February 2009

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Cited By

Zhou CZhang LWang YYu ZQian H(2014)A 4-bit CMOS phase shifter for millimeter-wave phased arraysAnalog Integrated Circuits and Signal Processing10.1007/s10470-014-0287-z79:3(461-468)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1007/s10470-014-0287-z
Tang TMurray ARoy S(2010)Methodology of statistical RTS noise analysis with charge-carrier trapping modelsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2010.204398857:5(1062-1070)Online publication date: 1-May-2010
https://dl.acm.org/doi/10.1109/TCSI.2010.2043988

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