MOESIL: a cache coherency protocol for locked mixed criticality L1 data cache
Article No.: 30, Pages 1 - 8
Abstract
The tremendous needs of computing power and predictive timing behaviours of modern systems bring revolutionary changes in memory subsystem architecture. One such improvement is the usage of locked caches to have predictive execution time. The existing cache coherence protocols such as MESI, MOSI, MOESI, and MESIF lack a comprehensive approach for handling coherency in locked caches. This work proposes MOESIL, an enhanced version of MOESI to increase the data consistency of locked caches. Experimental evaluations using splash-2 benchmark programs on CACTI 5.3 and CACOSIM simulator substantiate the suitability of MOESIL protocol for locked caches in multi-core mixed criticality systems to honour the deadline of high criticality jobs. It is observed that MOESIL protocol reduces the miss rate by 2.89% with a comparable energy consumption over MOESI protocol.
References
[1]
R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele, "Worst case delay analysis for memory interference in multicore systems," in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010.
[2]
G. Gracioli and A. A. Fröhlich, "On the influence of shared memory contention in real-time multicore applications," in 2014 Brazilian Symposium on Computing Systems Engineering. IEEE, 2014.
[3]
B. C. Ward, J. L. Herman, C. J. Kenna, and J. H. Anderson, "Outstanding paper award: Making shared caches more predictable on multicore platforms," in Real-Time Systems (ECRTS), 2013 25th Euromicro Conference on. IEEE, 2013.
[4]
I. Puaut and A. Arnaud, "Dynamic instruction cache locking in hard real-time systems," in Proc. of the 14th Int. Conference on Real-Time and Network Systems. Citeseer, 2006.
[5]
A. Awan, K. Bletsas, P. Souto, B. Åkesson, E. Tovar, and J. Ali, "Mixed-criticality scheduling with memory regulation," in 28th Euromicro Conference on Real-Time Systems. Euromicro Technical Committee on Real-Time Systems, 2016.
[6]
K. Bletsas, M. A. Awan, P. Souto, B. Åkesson, and E. Tovar, "Mixed-criticality systems with partial lockdown and cache reclamation upon mode change," in 29th Euromicro Conference on RTS, 2017.
[7]
D. P. Kaur and V. Sulochana, "Design and implementation of cache coherence protocol for high-speed multiprocessor system," in 2018 2nd IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2018.
[8]
G. Patil, N. B. Mallya, and B. K. Raveendran, "Moesif: a mc/mp cache coherence protocol with improved bandwidth utilisation," International Journal of Embedded Systems, vol. 11, no. 4, 2019.
[9]
N. Sritharan, A. Kaushik, M. Hassan, and H. Patel, "Enabling predictable, simultaneous and coherent data sharing in mixed criticality systems," in 2019 IEEE Real-Time Systems Symposium (RTSS). IEEE, 2019.
[10]
A. Kaushik, P. Tegegn, Z. Wu, and H. Patel, "Carp: A data communication mechanism for multi-core mixed-criticality systems," in 2019 IEEE RealTime Systems Symposium (RTSS). IEEE, 2019.
[11]
A. S. Nair, L. M. Colaco, G. Patil, B. K. Raveendran, and S. Punnekkatt, "Mediator-a mixed criticality deadline honored arbiter for multi-core realtime systems," in 2019 IEEE/ACM 23rd Int. Symposium on Distributed Simulation and Real Time Applications (DS-RT). IEEE, 2019.
[12]
J. L. Hennessy and D. A. Patterson, Computer architecture: a quantitative approach. Elsevier, 2011.
[13]
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The splash-2 programs: Characterization and methodological considerations," ACM SIGARCH computer architecture news, vol. 23, no. 2, pp. 24--36, 1995.
[14]
P. M. Ortego and P. Sack, "Sesc: Superescalar simulator," in 17 th Euro micro conference on real time systems (ECRTS'05). Citeseer, 2004.
[15]
D. Tarjan, S. Thoziyoor, and N. Jouppi, "Cacti 5.3," HP Laboratories Palo Alto Technical Report, 2005.
- MOESIL: a cache coherency protocol for locked mixed criticality L1 data cache
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Published In
September 2021
238 pages
ISBN:9781665433266
- General Chair:
- Carlos Tavares Calafate,
- Program Chair:
- Floriano De Rango
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- IEEE-CS\TCPP: TC on Parallel Processing
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IEEE Press
Publication History
Published: 11 January 2022
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- Research-article
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DS-RT '21
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DS-RT '21: International Symposium on Distributed Simulation and Real-Time Applications
September 27 - 29, 2021
Valencia, Spain
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