research-article

Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing

Author:

takayuki kawaharaAuthors Info & Claims

IEEE Design & Test, Volume 28, Issue 1

Pages 52 - 63

https://doi.org/10.1109/MDT.2010.97

Published: 01 January 2011 Publication History

Publisher Site

Abstract

Editor's note:Nonvolatile embedded memories may open the door to new computing paradigms based on "normally-off and instant-on" operation. This article covers recent trends of spin-transfer-torque RAM technology, an emerging class of nonvolatile memory, and discusses its impact on the different layers of computer system hierarchy.—Chris H. Kim, University of Minnesota

Cited By

View all

Zheng SHoseinzadeh MSwanson SHuang L(2023)TPFS: A High-Performance Tiered File System for Persistent Memories and DisksACM Transactions on Storage10.1145/358028019:2(1-28)Online publication date: 6-Mar-2023
https://dl.acm.org/doi/10.1145/3580280
Hu JChen JZhu YYang QPeng ZYu Y(2023)PMEH: A Parallel and Write-Optimized Extendible Hashing for Persistent MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327157942:11(3801-3814)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3271579
Wang YJia WJiang DXiong J(2023)A Survey of Non-Volatile Main Memory File SystemsJournal of Computer Science and Technology10.1007/s11390-023-1054-338:2(348-372)Online publication date: 30-Mar-2023
https://dl.acm.org/doi/10.1007/s11390-023-1054-3
Show More Cited By

Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing
1. Hardware
  1. Integrated circuits

Recommendations

Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)

Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (...
A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

We proposed a novel self-reference sensing scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) to overcome the large bit-to-bit variation of Magnetic Tunneling Junction (MTJ) resistance. Different from all the existing schemes, our solution ...
Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies

We propose a magnetic and electric level spin-transfer torque random access memory (STT-RAM) cell model to simulate the write operation of an STT-RAM. The model of a magnetic tunneling junction (MTJ) is modified to take into account the electrical ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

IEEE Design & Test Volume 28, Issue 1

January 2011

86 pages

ISSN:0740-7475

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 2011

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

26
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Zheng SHoseinzadeh MSwanson SHuang L(2023)TPFS: A High-Performance Tiered File System for Persistent Memories and DisksACM Transactions on Storage10.1145/358028019:2(1-28)Online publication date: 6-Mar-2023
https://dl.acm.org/doi/10.1145/3580280
Hu JChen JZhu YYang QPeng ZYu Y(2023)PMEH: A Parallel and Write-Optimized Extendible Hashing for Persistent MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327157942:11(3801-3814)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3271579
Wang YJia WJiang DXiong J(2023)A Survey of Non-Volatile Main Memory File SystemsJournal of Computer Science and Technology10.1007/s11390-023-1054-338:2(348-372)Online publication date: 30-Mar-2023
https://dl.acm.org/doi/10.1007/s11390-023-1054-3
Wu YLi L(2022)Zallocator: A High Throughput Write-Optimized Persistent Allocator for Non-Volatile MemoryACM Journal on Emerging Technologies in Computing Systems10.1145/354952818:4(1-20)Online publication date: 13-Oct-2022
https://dl.acm.org/doi/10.1145/3549528
Zou XWang FFeng DGuan TSu N(2022)ROWE-tree: A Read-Optimized and Write-Efficient B+-tree for Persistent MemoryProceedings of the 51st International Conference on Parallel Processing10.1145/3545008.3545043(1-11)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1145/3545008.3545043
Reidys BHuang JLee JAgrawal KSpear M(2022)Understanding and detecting deep memory persistency bugs in NVM programs with DeepMCProceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3503221.3508427(322-336)Online publication date: 2-Apr-2022
https://dl.acm.org/doi/10.1145/3503221.3508427
Shin DJang HOh KLee J(2022)An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main MemoryACM Transactions on Embedded Computing Systems10.1145/345199521:1(1-22)Online publication date: 14-Jan-2022
https://dl.acm.org/doi/10.1145/3451995
Zou XWang FFeng DZhu JXiao RSu N(2022)A write-optimal and concurrent persistent dynamic hashing with radix tree assistanceJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102462125:COnline publication date: 1-Apr-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2022.102462
Cai MHuang H(2021)A survey of operating system support for persistent memoryFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-020-9395-315:4Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1007/s11704-020-9395-3
Chen CWei QWong WWang C(2020)NV-Journaling: Locality-Aware Journaling Using Byte-Addressable Non-Volatile MemoryIEEE Transactions on Computers10.1109/TC.2019.294800469:2(288-299)Online publication date: 1-Feb-2020
https://dl.acm.org/doi/10.1109/TC.2019.2948004
Show More Cited By

Abstract

Cited By

Recommendations

Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)

A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)

Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies

Comments

Information

Published In

Publisher

Publication History

Author Tags

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations