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Applying AnalogTechniques in Digital CMOS Buffers to ImproveSpeed and Noise Immunity

Authors:

Radu M. Secareanu,

Eby G. FriedmanAuthors Info & Claims

Analog Integrated Circuits and Signal Processing, Volume 27, Issue 3

Pages 273 - 277

https://doi.org/10.1023/A:1011257908593

Published: 01 June 2001 Publication History

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Abstract

A digital CMOS buffer circuit with a voltage transfer characteristic (VTC) with low threshold voltage detection, hysteresis, and high noise immunity is presented. The circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty, offering at the same time high noise immunity to glitches induced either through capacitive coupling or from the power supply lines. The high noise immunity of the proposed buffer circuit is achieved using differential mode rejection and a differential redundant circuit architecture.

References

[1]

1. Secareanu, R. M., Adler, V., and Friedman, E. G., "Exploiting hysteresis in a CMOS buffer," in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 205- 208, September 1999.

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[2]

2. Adler, V. and Friedman, E. G., "Repeater design to reduce delay and power in resistive interconnect." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing CAS II-45(5), May 1998.

Google Scholar

[3]

3. Adler, V. and Friedman, E. G., "Repeater insertion to reduce delay and power in RC tree structures," in Proceedings of the Asilomar Conference on Signals, Systems, and Computers, pp. 749-752, November 1997.

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Applying AnalogTechniques in Digital CMOS Buffers to ImproveSpeed and Noise Immunity
1. Hardware

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Published In

cover image Analog Integrated Circuits and Signal Processing

Analog Integrated Circuits and Signal Processing Volume 27, Issue 3

June 2001

200 pages

ISSN:0925-1030

Editors:
Mohammed Ismail
Ohio State Univ., Columbus
,
David G. Haigh
Univ. College, London, UK
,
Nobuo Fujii
Tokyo Institute of Technology, Meguro-ku, Tokyo, Japan

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Kluwer Academic Publishers

United States

Publication History

Published: 01 June 2001

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A CMOS low noise amplifier with employing noise cancellation and modified derivative superposition technique

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A CMOS low noise amplifier with employing noise cancellation and modified derivative superposition technique

5.18---7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

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