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Limits of Using Signatures for Permutation Independent Boolean Comparison

Published: 01 September 2002 Publication History

Abstract

This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations. The permutation problem has several applications in the synthesis and verification of combinational logic: it arises in the technology mapping stage of logic synthesis and in logic verification. A popular method to solve it is to compute a signature for each variable that helps to establish a correspondence between the variables. Several researchers have suggested a wide range of signatures that have been used for this purpose. However, for each choice of signature, there remain variables that cannot be uniquely identified. Our research has shown that, for a given example, this set of problematic variables tends to be the same–regardless of the choice of signatures. The paper investigates this problem.

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Cited By

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  • (2014)Template-based circuit understandingProceedings of the 14th Conference on Formal Methods in Computer-Aided Design10.5555/2682923.2682943(83-90)Online publication date: 21-Oct-2014
  • (2014)A universal symmetry detection algorithmProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617039(1-4)Online publication date: 24-Mar-2014
  • (2012)Extending symmetric variable-pair transitivities using state-space transformationsProceedings of the great lakes symposium on VLSI10.1145/2206781.2206859(315-320)Online publication date: 3-May-2012
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Information

Published In

cover image Formal Methods in System Design
Formal Methods in System Design  Volume 21, Issue 2
September 2002
133 pages

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 September 2002

Author Tags

  1. high level design tools
  2. permutation independent Boolean comparison
  3. reduced ordered binary decision diagram
  4. synthesis and verification

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View all
  • (2014)Template-based circuit understandingProceedings of the 14th Conference on Formal Methods in Computer-Aided Design10.5555/2682923.2682943(83-90)Online publication date: 21-Oct-2014
  • (2014)A universal symmetry detection algorithmProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617039(1-4)Online publication date: 24-Mar-2014
  • (2012)Extending symmetric variable-pair transitivities using state-space transformationsProceedings of the great lakes symposium on VLSI10.1145/2206781.2206859(315-320)Online publication date: 3-May-2012
  • (2011)Conjugate symmetryFormal Methods in System Design10.1007/s10703-011-0116-238:3(263-288)Online publication date: 1-Jun-2011
  • (2006)Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiabilityProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147044(510-515)Online publication date: 24-Jul-2006
  • (2006)Fast Boolean Matching with Don't CaresProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.65(346-351)Online publication date: 27-Mar-2006

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