An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection

Lattice Reduction aided MIMO detectors have been demonstrated to offer a promising gain by providing near-optimal performance. This paper presents a C-programmable ASIP baseband processor, for near-optimal MIMO detection targeting a 4 4 LTE system. The detector supports multiple MIMO detection modes, with both hard and soft output. In order to improve implementation efficiency, the previously reported MIMO detection algorithm Multi-Tree Selective Spanning Detector (MTSS) is modified to use orthogonal real-valued decomposition (ORVD). Afterwards, a low-complexity log-likelihood-ratio (LLR) improvement technique called counter-ML bit-flipping algorithm is proposed. The proposed LLR generation algorithm has been designed to take advantage of MTSS, by maximizing the reuse of computations. Performance of the proposed solution can be tuned ranging from SIC to near-ML to near-MAP. The baseband processor is designed using 40 nm process technology with an equivalent gate-count (GE) of 68.41 kGE. Operating at 600 MHz for a 4 4 QAM-64 LTE system, the processor delivers peak-throughputs of 3.6 Gbps and 2.05 Gbps in case of hard and soft output MIMO detection, with 13.03 mW and 22.99 mW respective power consumption. The corresponding energy efficiency is 3.61 pJ/bit and 11.17 pJ/bit. In terms of energy efficiency, the proposed reconfigurable solution is comparable to recently reported ASIC MIMO detectors, while providing multiple-modes of operation and the flexilibility of C-programming.