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Exploiting multi-cycle false paths in the performance optimization of sequential circuits

Authors:

Pranav Ashar,

Sujit Dey,

Sharad MalikAuthors Info & Claims

ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Pages 510 - 517

Published: 08 November 1992 Publication History

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References

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Cited By

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D'Silva VKroening DBenini LDe Micheli GAl-Hashimi BMueller W(2009)Fixed points for multi-cycle path detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875027(1710-1715)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875027
Yang KCheng KHirose F(2006)Efficient identification of multi-cycle false pathProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118390(360-365)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118390
Papachristou CNourani MSymonds GNebel W(1996)False path exclusion in delay analysis of RTL-based datapath-controller designsProceedings of the conference on European design automation10.5555/252471.252530(336-341)Online publication date: 20-Sep-1996
https://dl.acm.org/doi/10.5555/252471.252530
Show More Cited By

Index Terms

Exploiting multi-cycle false paths in the performance optimization of sequential circuits
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Information

Published In

ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

November 1992

637 pages

ISBN:0897915402

Chairmen:
Louise Trevillyan
IBM Corp., Yorktown Heights, NY
,
Michael Lightner
Univ. of Colorado, Boulder

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 08 November 1992

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all

D'Silva VKroening DBenini LDe Micheli GAl-Hashimi BMueller W(2009)Fixed points for multi-cycle path detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875027(1710-1715)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875027
Yang KCheng KHirose F(2006)Efficient identification of multi-cycle false pathProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118390(360-365)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118390
Papachristou CNourani MSymonds GNebel W(1996)False path exclusion in delay analysis of RTL-based datapath-controller designsProceedings of the conference on European design automation10.5555/252471.252530(336-341)Online publication date: 20-Sep-1996
https://dl.acm.org/doi/10.5555/252471.252530
Hasan ZCiesielski M(1995)Elimination of multi-cycle false paths by state encodingProceedings of the 1995 European conference on Design and Test10.5555/787258.787430Online publication date: 6-Mar-1995
https://dl.acm.org/doi/10.5555/787258.787430
Saldanha AHarkness HMcGeer PBrayton RSangiovanni-Vincentelli ALorenzetti M(1994)Performance optimization using exact sensitizationProceedings of the 31st annual Design Automation Conference10.1145/196244.196448(425-429)Online publication date: 6-Jun-1994
https://dl.acm.org/doi/10.1145/196244.196448
Gupta ASiewiorek DLorenzetti M(1994)Automated multi-cycle symbolic timing verification of microprocessor-based designsProceedings of the 31st annual Design Automation Conference10.1145/196244.196299(113-119)Online publication date: 6-Jun-1994
https://dl.acm.org/doi/10.1145/196244.196299
Lam WBrayton RSangiovanni-Vincentelli ALorenzetti M(1994)Exact minimum cycle times for finite state machinesProceedings of the 31st annual Design Automation Conference10.1145/196244.196294(100-105)Online publication date: 6-Jun-1994
https://dl.acm.org/doi/10.1145/196244.196294

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Multi-threshold voltage FinFET sequential circuits

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Exploiting multicycle false paths in the performance optimization of sequential logic circuits