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High-level synthesis and codesign methods: an application to a videophone codec

Authors:

Jean-Claude HerluisonAuthors Info & Claims

EURO-DAC '95/EURO-VHDL '95: Proceedings of the conference on European design automation

Pages 444 - 451

Published: 01 December 1995 Publication History

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Cited By

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Coste PHessel FLe Marrec PSugar ZRomdhani MSuescun RZergainoh NJarraya AJerraya ALavagno LVahid F(1999)Multilanguage design of heterogeneous systemsProceedings of the seventh international workshop on Hardware/software codesign10.1145/301177.301206(54-58)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1145/301177.301206
Jemai AKission PJerraya ADewilde PRammig FMusgrave G(1998)Architectural simulation in the context of behavioral synthesisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368303(590-595)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368303
Liem CNaçabal FValderrama CPaulin PJerraya A(1997)System-on-a-Chip Cosimulation and CompilationIEEE Design & Test10.1109/54.58773614:2(16-25)Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.1109/54.587736
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High-level synthesis and codesign methods: an application to a videophone codec

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Information

Published In

EURO-DAC '95/EURO-VHDL '95: Proceedings of the conference on European design automation

December 1995

640 pages

ISBN:0818671564

Chairman:
Gerald Musgrave
Brunel Univ., Uxbridge, Middlesex, UK

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 December 1995

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EuroDAC95

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SIGDA

EuroDAC95: European Design Automation Conference

September 18 - 22, 1995

Brighton, England

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Cited By

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Coste PHessel FLe Marrec PSugar ZRomdhani MSuescun RZergainoh NJarraya AJerraya ALavagno LVahid F(1999)Multilanguage design of heterogeneous systemsProceedings of the seventh international workshop on Hardware/software codesign10.1145/301177.301206(54-58)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1145/301177.301206
Jemai AKission PJerraya ADewilde PRammig FMusgrave G(1998)Architectural simulation in the context of behavioral synthesisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368303(590-595)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368303
Liem CNaçabal FValderrama CPaulin PJerraya A(1997)System-on-a-Chip Cosimulation and CompilationIEEE Design & Test10.1109/54.58773614:2(16-25)Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.1109/54.587736
Liem CPaulin PJerraya A(1997)Compilation Methods for the Address Calculation Units of Embedded Processor SystemsDesign Automation for Embedded Systems10.1023/A:10088625108772:1(61-77)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.1023/A%3A1008862510877
Valderrama CNacabal FPaulin PJerraya A(1996)Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systemsProceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)10.5555/827259.828050Online publication date: 19-Jun-1996
https://dl.acm.org/doi/10.5555/827259.828050
Berrebi EKission PVernalde SDe Troch SHerluison JFréhel JJerraya ABolsens IPennino TYoffa E(1996)Combined control flow dominated and data flow dominated high-level synthesisProceedings of the 33rd annual Design Automation Conference10.1145/240518.240627(573-578)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240627

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High-level synthesis: an essential ingredient for designing complex ASICs

High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

Layout-driven RTL binding techniques for high-level synthesis