Browse Theses

While there is a trend to add more functionality onto chips in the form of entire systems-on-a-chip (SOC), high-level design languages and tools are needed to reduce the design time. With the rapidly advanced technology and the greatly increased integration density and clock frequency, the power requirements keep increasing, hence EDA tools are needed to assist customers to design chips with low power.

This dissertation presents the PACT compiler which solves the above two problems: (1) it allows users to develop algorithms in a high level language, namely C, and generate HDL codes that can be synthesized onto FPGAs or ASICs; (2) it explicitly addresses low power issues during the high-level synthesis stages.

Since IP cores can improve the flexibility, precision and robust of the hardware design, an IP core library is generated based on Xilinx FPGA together with the methods for integrating IP cores into PACT compiler. To increase the estimation speed and accuracy, an equation-based macro-modeling technique is also introduced. Those area, delay and power models are very accurate and efficient.

To explore the parallelism and concurrency of the design, a CDFG framework is generated from HDL AST. Within this framework, a lot of high-level synthesis techniques are developed. These optimization techniques include ASAP, ALAP, RSASAP, RSALAP, ETAIP, TPAIP and register sharing and binding.

To test the correctness of the HDL compiler, a simulation and verification method is designed. FPGA power estimation flow is also provided to show the improvement of the optimization algorithms. Experimental results show that the PACT compiler works correctly and efficiently.