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Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

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ISLPED '96: Proceedings of the 1996 international symposium on Low power electronics and design

Pages 353 - 358

Published: 12 August 1996 Publication History

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Cited By

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Cheng KLin TChang R(2009)Profile-based dynamic pipeline scalingThe Journal of Supercomputing10.1007/s11227-008-0224-y48:2(210-226)Online publication date: 1-May-2009
https://dl.acm.org/doi/10.1007/s11227-008-0224-y
Cheng KLin TChang R(2007)Compiler support for dynamic pipeline scalingProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780754(64-74)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.5555/1780745.1780754
Chandar SMehendale MGovindarajan R(2006)Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable EncodingJournal of VLSI Signal Processing Systems10.1007/s11265-006-8538-644:3(245-267)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1007/s11265-006-8538-6
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Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
1. Hardware

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Published In

ISLPED '96: Proceedings of the 1996 international symposium on Low power electronics and design

August 1996

390 pages

ISBN:0780335716

Publisher

IEEE Press

Publication History

Published: 12 August 1996

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ISLPED96

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SIGDA
IEEE-SSCS
IEEE-CAS

ISLPED96: 1996 International Symposium on Low Power Electronics & Design

August 12 - 14, 1996

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Cheng KLin TChang R(2009)Profile-based dynamic pipeline scalingThe Journal of Supercomputing10.1007/s11227-008-0224-y48:2(210-226)Online publication date: 1-May-2009
https://dl.acm.org/doi/10.1007/s11227-008-0224-y
Cheng KLin TChang R(2007)Compiler support for dynamic pipeline scalingProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780754(64-74)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.5555/1780745.1780754
Chandar SMehendale MGovindarajan R(2006)Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable EncodingJournal of VLSI Signal Processing Systems10.1007/s11265-006-8538-644:3(245-267)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1007/s11265-006-8538-6
John JHu JZiavras S(2005)Optimizing the Thermal Behavior of Subarrayed Data CachesProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.81(625-630)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.81
Hu JVijaykrishnan NKim SKandemir MIrwin M(2004)Scheduling Reusable Instructions for Power ReductionProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969092Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969092
Bajwa RSchumann NKojima HBarton BPedram MChandrakasan AKiaei S(1997)Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSPProceedings of the 1997 international symposium on Low power electronics and design10.1145/263272.263309(137-142)Online publication date: 1-Aug-1997
https://dl.acm.org/doi/10.1145/263272.263309

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Code optimization of pipeline constraints

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Tuning the continual flow pipeline architecture with virtual register renaming