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Design of storage hierarchy in multithreaded architectures

Authors:

Lucas Roh,

Walid A. NajjarAuthors Info & Claims

MICRO 28: Proceedings of the 28th annual international symposium on Microarchitecture

Pages 271 - 278

Published: 01 December 1995 Publication History

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References

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Cited By

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Kyriacou CEvripidou PTrancoso P(2006)Data-Driven Multithreading Using Conventional MicroprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2006.13617:10(1176-1188)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1109/TPDS.2006.136
Kiemb MChoi KIrwin MZhao WLavagno LMahlke S(2004)Memory and architecture exploration with thread shifting for multithreaded processors in embedded systemsProceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1023833.1023865(230-237)Online publication date: 22-Sep-2004
https://dl.acm.org/doi/10.1145/1023833.1023865
Gaudiot JDeBoni TFeo JBöhm WNajjar WMiller P(2001)The Sisal projectCompiler optimizations for scalable parallel systems10.5555/380466.380468(45-72)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/380466.380468
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Design of storage hierarchy in multithreaded architectures

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Information & Contributors

Information

Published In

MICRO 28: Proceedings of the 28th annual international symposium on Microarchitecture

December 1995

343 pages

ISBN:0818673494

Chairmen:
Trevor Mudge
The Univ. of Michigan, Ann Arbor, MI
,
Kemal Ebcioğlu
IBM T. J. Watson Research Center, Yorktown Heights, NY

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 December 1995

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Conference

MICRO95

Sponsor:

SIGMICRO
IEEE-CS\TCMM

MICRO95: 28th Annual IEEE/ACM International Symposium on Microarchitecture

November 29 - December 1, 1995

Michigan, Ann Arbor, USA

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

View all

Kyriacou CEvripidou PTrancoso P(2006)Data-Driven Multithreading Using Conventional MicroprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2006.13617:10(1176-1188)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1109/TPDS.2006.136
Kiemb MChoi KIrwin MZhao WLavagno LMahlke S(2004)Memory and architecture exploration with thread shifting for multithreaded processors in embedded systemsProceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1023833.1023865(230-237)Online publication date: 22-Sep-2004
https://dl.acm.org/doi/10.1145/1023833.1023865
Gaudiot JDeBoni TFeo JBöhm WNajjar WMiller P(2001)The Sisal projectCompiler optimizations for scalable parallel systems10.5555/380466.380468(45-72)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/380466.380468
Gaudiot JDeBoni TFeo JBöhm WNajjar WMiller P(1997)The Sisal Model of Functional Programming and its ImplementationProceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis10.5555/523978.826095Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/523978.826095

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Compiling for multithreaded architectures

Design hierarchy-guided multilevel circuit partitioning