Soft-edge flip-flops for improved timing yield: design and optimization

Parameter variations cause high yield losses due to their large impact on circuit delay. In this paper, we propose the use of so-called soft-edge flip-flops as an effective way to mitigate these yield losses. Soft-edge flip-flops have a small window of transparency (ranging from 0.25-3 FO4) instead of a hard edge, allowing limited cycle stealing on critical paths, and thus compensating for delay variations. By enabling time borrowing, soft-edge flip-flops allow random delay variations to average out across multiple logic stages. In addition, they address small amounts of delay imbalance between logic stages, further maximizing the frequency of operation. We develop a library of soft-edge flip-flops with varying amounts of softness. We show that the power and area overhead of soft-edge flip-flops grows directly with the amount of softness. We then propose a statistically aware flip-flop assignment algorithm that maximizes the gain in timing yield while minimizing the incurred power overhead. Experimental results on a wide range of benchmark circuits show that the proposed approach improves the mean delay by 1.9--22.3% while simultaneously reducing the standard deviation of delay by 1.9--24.1% while increasing power by a small amount (0.3--2.8%).