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An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

Published: 27 January 2004 Publication History

Abstract

In this paper, we propose a fast algorithm to construct a performance driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Recently several algorithms [1, 2, 3, 4] have been published addressing the routing tree construction problem. But all these algorithms are slow and not scalable. In this paper we propose an algorithm which is fast and scalable with problem size. The main idea of our approach is to specify some important high-level features of the whole routing tree so that it can be broken down into several components. We apply stochastic search to find the best specification. Since we need very few high-level features, the size of stochastic search space is small which can be searched in very less time. The solutions for the components are either pre-generated and stored in lookup tables, or generated by extremely fast algorithms whenever needed. Since it is efficient to obtain solutions for components, it is also efficient to construct and evaluate the whole routing tree for each specification. Experimental results show that, for trees of moderate size, our algorithm is at least several hundred times faster than the recently proposed algorithms [3, 4]. Experimental results also show that the trees generated by our algorithm have almost same delay and resource consumption as the trees generated by SP-Tree.

References

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J. Lillis, C. K. Cheng, T. T. Lin, C. Y. Ho, "Performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing", in Proc. ACM/IEEE Design Automation Conf., 1996, 395--400.
[2]
M. Hrkic, J. Lillis "S-Tree: A technique for Buffered routing tree synthesis", SASIMI, 2001, pp. 242--249.
[3]
M. Hrkic, J. Lillis, "Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages", in Proc. Int. Symp. Physical Design., 2002, pp. 98--103.
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X. Tang, R. Tian, H. Xiang, and D. Wong, "A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints" in Proc. Int. Conf. Computer-Aided Design., 2001, pp. 49--56.
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J. Hu, C. Alpert, S. T. Quay, and G. Gandham, "Buffer Insertion with Adaptive Blockage Avoidance", in Proc. Int. Symp. Physical Design., 2002, pp. 92--97.
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Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest, "Introduction to Algorithms", Prentice - Hall, 1997.
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R. Otten and R. Brayton, "Planning for performance" in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 122--127.
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Cien Shen and Chris Chu, "Bounds on Number of Slicing, Mosaic, and General Floorplans", IEEE TCAD, Vol. 22, No. 10, October 2003.
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C. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap, S. Quay, "Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique", IEEE TCAD, 2004.
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J. Lillis, C. K. Cheng, and T. T. Y. Lin, "Opitmal wire sizing and buffer insertion for low power and a generalized delay model", in Proc Int. Conf. Computer-Aided Design., 1996, pp. 134--139.

Cited By

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  • (2005)An efficient surface-based low-power buffer insertion algorithmProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055155(86-93)Online publication date: 3-Apr-2005
  1. An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

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    ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference
    January 2004
    957 pages
    ISBN:0780381750

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    Published: 27 January 2004

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    • (2005)An efficient surface-based low-power buffer insertion algorithmProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055155(86-93)Online publication date: 3-Apr-2005

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