[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.5555/996070.1009917acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
Article

Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters

Published: 09 November 2003 Publication History

Abstract

In this paper a general method to design a pipelined ADC withminimum power consumption is presented. By expressing the totalpower consumption and the total input-referred noise of theconverter as functions of the capacitor values and the resolutions ofthe converter stages, an optimization algorithm is employed tocalculate the optimum values of these parameters, which lead tominimum power consumption while a specific noise requirement issatisfied. To determine the bias current values of operationalamplifiers an optimal choice for settling and slewing timeparameters is proposed. A practical design example is presented toshow the effectiveness of the proposed methodology.

References

[1]
{1} S.H. Lewis, "Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications," IEEE Trans. Circuits & Systems-II, Vol. 39, No. 8, pp. 516-523, Aug. 1992.
[2]
{2} J. Goes, et. al, "Systematic design for optimization of high-speed self-calibrated pipelined A/D converters," in IEEE Trans. On Circuits & Systems-II, vol. 45, pp. 1513-1526, Dec. 1998.
[3]
{3} P.T.F. Kwok, H.C. Leung, "Power optimization for pipeline analog-to-digital converters," in IEEE Trans. On Circuits & Systems-II, vol. 46, pp. 549-53, May 1999.
[4]
{4} M. Hershenson, "Design of pipeline analog-to-digital converters via geometric programming," in Proc. of IEEE Intl. Conf. on Computer Aided Design, ICCAD 2002.
[5]
{5} R. Lotfi, M. Taherzadeh-S., M.Y. Azizi, O. Shoaie, "A low-power design methodology for high-resolution pipelined analog-to-digital converters," in Proc. of ACM/IEEE Intl. Symp. on Low-Power Electronics and Design, ISLPED'03, Aug. 2003.
[6]
{6} B. Razavi, Design of Analog CMOS Integrated Circuits, Mc.Graw-Hill, 2001.
[7]
{7} M. Waltari, Circuit techniques for low-voltage and high-speed A/D converters, PhD. Dissertation, Helsinki Univ. of Tech., 2002.
[8]
{8} K. Bult, G. Geelen, "A fast-settling CMOS opamp for SC circuits with 90-dB DC gain" in IEEE Journal of Solid-State Circuits, vol. 25, pp. 1379-84, Dec. 1990.
[9]
{9} S. Rabii, B. Wooley, "A 1.8-V digital-audio sigma-delta modulator in 0.8-µm CMOS," in IEEE Journal of Solid-State Circuits, vol. 32, pp. 783-796, Jun. 1997.
[10]
{10} Hui Pan, et.al, "A 3.3-V 12-b 50-MS/s A/D Converter in 0.6- um CMOS with over 80-dB SFDR," in IEEE Journal of Solid-State Circuits, Vol. 35, No. 12, pp. 1769-80, Dec. 2000.
[11]
{11} H. van der Ploeg, et. al, "A 2.5-V 12-b 54-Msample/s 0.25-um CMOS ADC in 1-mm2 With Mixed-Signal Chopping and Calibration," in IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, Dec. 2001.
[12]
{12} A. Shabra and H.-S. Lee, "A 12-bit Mismatch-Shaped Pipeline A/D Converter," Digest of Technical Papers, IEEE Symposium on VLSI Circuits, pp. 211-214, 2001.
[13]
{13} A. Loloee, et. al, "A 12bit 80MSps pipelined ADC core with 190mW consumption from 3V in 0.18µm digital CMOS," in Proc. European Solid-State circuits conference, ESSCIRC 2002, Florence, Italy, pp. 467-470.

Cited By

View all
  • (2006)A power optimized design methodology for low-distortion sigma-delta-pipeline ADCsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127974(284-289)Online publication date: 30-Apr-2006

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
November 2003
899 pages
ISBN:1581137621

Sponsors

Publisher

IEEE Computer Society

United States

Publication History

Published: 09 November 2003

Check for updates

Qualifiers

  • Article

Conference

ICCAD03
Sponsor:

Acceptance Rates

ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 13 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2006)A power optimized design methodology for low-distortion sigma-delta-pipeline ADCsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127974(284-289)Online publication date: 30-Apr-2006

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media