• Deligiannis N, Faller T, Guglielminetti I, Cantoro R, Becker B and Reorda M. (2023). Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors 2023 IEEE 32nd Asian Test Symposium (ATS). 10.1109/ATS59501.2023.10317988. 979-8-3503-0310-0. (1-6).

    https://ieeexplore.ieee.org/document/10317988/

  • Bagbaba A, Augusto da Silva F, Sonza Reorda M, Hamdioui S, Jenihhin M and Sauer C. (2022). Automated Identification of Application-Dependent Safe Faults in Automotive Systems-on-a-Chips. Electronics. 10.3390/electronics11030319. 11:3. (319).

    https://www.mdpi.com/2079-9292/11/3/319

  • Deligiannis N, Cantoro R, Sauer M, Becker B and Reorda M. (2021). New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core 2021 IEEE 39th VLSI Test Symposium (VTS). 10.1109/VTS50974.2021.9441040. 978-1-6654-1949-9. (1-7).

    https://ieeexplore.ieee.org/document/9441040/

  • Gursoy C, Jenihhin M, Oyeniran A, Piumatti D, Raik J, Reorda M and Ubar R. (2019). New categories of Safe Faults in a processor-based Embedded System 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 10.1109/DDECS.2019.8724642. 978-1-7281-0073-9. (1-4).

    https://ieeexplore.ieee.org/document/8724642/

  • Cantoro R, Carbonara S, Floridia A, Sanchez E, Sonza Reorda M and Mess J. (2019). Improved Test Solutions for COTS-Based Systems in Space Applications. VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms. 10.1007/978-3-030-23425-6_10. (187-206).

    https://link.springer.com/10.1007/978-3-030-23425-6_10

  • Cantoro R, Carbonara S, Floridia A, Sanchez E, Reorda M and Mess J. (2018). An analysis of test solutions for COTS-based systems in space applications 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). 10.1109/VLSI-SoC.2018.8644846. 978-1-5386-4756-1. (59-64).

    https://ieeexplore.ieee.org/document/8644846/

  • Hosokawa T, Niseki M, Yoshimura M, Yamazaki H, Arai M, Yotsuyanagi H and Hashizume M. (2018). A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 10.1109/IOLTS.2018.8474268. 978-1-5386-5992-2. (43-46).

    https://ieeexplore.ieee.org/document/8474268/

  • Bernardeschi C, Cassano L, Domenici A and Sterpone L. (2016). UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. Integration. 10.1016/j.vlsi.2016.03.004. 55. (85-97). Online publication date: 1-Sep-2016.

    https://linkinghub.elsevier.com/retrieve/pii/S0167926016300037

  • Cassano L. (2014). Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs 2014 IEEE International Test Conference (ITC). 10.1109/TEST.2014.7035366. 978-1-4799-4722-5. (1-10).

    http://ieeexplore.ieee.org/document/7035366/

  • Bernardeschi C, Cassano L and Domenici A. (2013). Formal approaches to SEU testing in FPGAs 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). 10.1109/AHS.2013.6604248. 978-1-4673-6383-9. (209-216).

    http://ieeexplore.ieee.org/document/6604248/

  • Bernardeschi C, Cassano L, Domenici A and Sterpone L. Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI. (7-12).

    https://doi.org/10.1145/2483028.2483050

  • Viilukas T, Karputkin A, Raik J, Jenihhin M, Ubar R and Fujiwara H. (2012). Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. Journal of Electronic Testing: Theory and Applications. 28:4. (511-521). Online publication date: 1-Aug-2012.

    https://doi.org/10.1007/s10836-012-5312-5

  • Bernardeschi C, Cassano L and Domenici A. SEU-X. Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012). (25-30).

    https://doi.org/10.1109/IOLTS.2012.6313836

  • Raik J, Rannaste A, Jenihhin M, Viilukas T, Ubar R and Fujiwara H. Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. Proceedings of the 2011 Sixteenth IEEE European Test Symposium. (147-152).

    https://doi.org/10.1109/ETS.2011.38

  • Raik J, Fujiwara H, Ubar R and Krivenko A. Untestable Fault Identification in Sequential Circuits Using Model-Checking. Proceedings of the 2008 17th Asian Test Symposium. (21-26).

    https://doi.org/10.1109/ATS.2008.22

  • Raik J, Ubar R, Krivenko A and Kruus M. (2007). Hierarchical Identification of Untestable Faults in Sequential Circuits 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). 10.1109/DSD.2007.4341539. 0-7695-2978-X. (668-671).

    http://ieeexplore.ieee.org/document/4341539/

  • Yu X and Abramovici M. (2006). Sequential circuit ATPG using combinational algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24:8. (1294-1310). Online publication date: 1-Nov-2006.

    https://doi.org/10.1109/TCAD.2005.850835

  • Syal M and Hsiao M. (2006). New techniques for untestable fault identification in sequential circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:6. (1117-1131). Online publication date: 1-Jun-2006.

    https://doi.org/10.1109/TCAD.2005.855967

  • Hsiao M. (2006). Test Generation. VLSI Test Principles and Architectures. 10.1016/B978-012370597-6/50008-1. (161-262).

    http://linkinghub.elsevier.com/retrieve/pii/B9780123705976500081

  • Syal M and Hsiao M. Untestable fault identification using recurrence relations and impossible value assignments . 17th International Conference on VLSI Design. 10.1109/ICVD.2004.1260967. 0-7695-2072-3. (481-486).

    http://ieeexplore.ieee.org/document/1260967/

  • Bareiša E, Motiejūnas K and Šeinauskas R. (2003). Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation. Informatica. 14:2. (135-154). Online publication date: 1-Apr-2003.

    /doi/10.5555/1413485.1413486

  • Syal M and Hsiao M. A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. Proceedings of the conference on Design, Automation and Test in Europe - Volume 1.

    /doi/10.5555/789083.1022744

  • Syal M and Hsiao M. A novel, low-cost algorithm for sequentially untestable fault identification 6th Design Automation and Test in Europe (DATE 03). 10.1109/DATE.2003.1253626. 0-7695-1870-2. (316-321).

    http://ieeexplore.ieee.org/document/1253626/

  • Abramovici M, Yu X and Rudnick E. Low-cost sequential ATPG with clock-control DFT. Proceedings of the 39th annual Design Automation Conference. (243-248).

    https://doi.org/10.1145/513918.513983

  • Abrarnovici M, Xiaoming Yu and Rudnick E. (2002). Low-cost sequential ATPG with clock-control DFT Proceedings of 39th Design Automation Conference. 10.1109/DAC.2002.1012629. 1-58113-461-4. (243-248).

    http://ieeexplore.ieee.org/document/1012629/