• Zhong Y, Yu T, Yang K and Fang S. Via Pillar-aware Detailed Placement. Proceedings of the 2020 International Symposium on Physical Design. (17-24).

    https://doi.org/10.1145/3372780.3375561

  • Lin Y, Li W, Gu J, Ren H, Khailany B and Pan D. ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10.1109/TCAD.2020.2971531. (1-1).

    https://ieeexplore.ieee.org/document/8982049/

  • Mak W, Kuo W, Zhang S, Lei S and Chu C. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10.1109/TCAD.2017.2661819. 36:7. (1103-1112).

    http://ieeexplore.ieee.org/document/7837646/

  • Lin Y, Yu B, Xu B and Pan D. Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10.1109/TCAD.2017.2648843. 36:7. (1140-1152).

    http://ieeexplore.ieee.org/document/7807206/

  • Debacker P, Han K, Kahng A, Lee H, Raghavan P and Wang L. Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. Proceedings of the 54th Annual Design Automation Conference 2017. (1-6).

    https://doi.org/10.1145/3061639.3062338

  • Lin Y, Yu B, Zou Y, Li Z, Alpert C and Pan D. (2017). Stitch aware detailed placement for multiple E-beam lithography. Integration. 10.1016/j.vlsi.2017.02.004. 58. (47-54). Online publication date: 1-Jun-2017.

    https://linkinghub.elsevier.com/retrieve/pii/S0167926017300901

  • Lin Y, Yu B and Pan D. (2016). Detailed placement in advanced technology nodes: A survey 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). 10.1109/ICSICT.2016.7999056. 978-1-4673-9717-9. (836-839).

    http://ieeexplore.ieee.org/document/7999056/

  • Tseng K, Chang Y and Liu C. Minimum-implant-area-aware detailed placement with spacing constraints. Proceedings of the 53rd Annual Design Automation Conference. (1-6).

    https://doi.org/10.1145/2897937.2898045

  • Kuang J, Chow W and Young E. Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10.1109/TVLSI.2015.2461463. 24:4. (1319-1332).

    http://ieeexplore.ieee.org/document/7208898/

  • Lei S, Mak W and Chu C. (2016). Minimum implant area-aware placement and threshold voltage refinement 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). 10.1109/ASPDAC.2016.7428010. 978-1-4673-9569-4. (192-197).

    http://ieeexplore.ieee.org/document/7428010/

  • Yibo Lin , Yu B, Yi Zou , Li Z, Alpert C and Pan D. (2016). Stitch aware detailed placement for multiple e-beam lithography 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). 10.1109/ASPDAC.2016.7428009. 978-1-4673-9569-4. (186-191).

    http://ieeexplore.ieee.org/document/7428009/

  • Yu B and Pan D. (2016). Conclusions and Future Works. Design for Manufacturability with Advanced Lithography. 10.1007/978-3-319-20385-0_6. (159-162).

    https://link.springer.com/10.1007/978-3-319-20385-0_6

  • Lin Y, Yu B, Xu B and Pan D. Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. (396-403).

    /doi/10.5555/2840819.2840875

  • Lin Y, Yu B, Xu B and Pan D. (2015). Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 10.1109/ICCAD.2015.7372597. 978-1-4673-8388-2. (396-403).

    http://ieeexplore.ieee.org/document/7372597/

  • Pan D, Liebmann L, Yu B, Xu X and Lin Y. Pushing multiple patterning in sub-10nm. Proceedings of the 52nd Annual Design Automation Conference. (1-6).

    https://doi.org/10.1145/2744769.2747940