• Wang C, Tu T, Qin S, Wu G, Gao F and Wan M. (2024). Understanding Atomics and Memory Ordering Issues in Real-World Rust Software 2024 IEEE 35th International Symposium on Software Reliability Engineering (ISSRE). 10.1109/ISSRE62328.2024.00061. 979-8-3503-5388-4. (582-592).

    https://ieeexplore.ieee.org/document/10771495/

  • Klimiankou Y. Towards practical multikernel OSes with MySyS. Proceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems. (29-37).

    https://doi.org/10.1145/3546591.3547525

  • (2022). Bibliography. Storage Systems. 10.1016/B978-0-32-390796-5.00023-1. (641-693).

    https://linkinghub.elsevier.com/retrieve/pii/B9780323907965000231

  • Thomasian A. (2022). Introduction. Storage Systems. 10.1016/B978-0-32-390796-5.00010-3. (1-87).

    https://linkinghub.elsevier.com/retrieve/pii/B9780323907965000103

  • (2021). References. Microprocessor 4. 10.1002/9781119801979.refs. (197-210). Online publication date: 1-Feb-2021.

    https://onlinelibrary.wiley.com/doi/10.1002/9781119801979.refs

  • (2020). References. Microprocessor 3. 10.1002/9781119788010.refs. (179-191). Online publication date: 30-Nov-2020.

    https://onlinelibrary.wiley.com/doi/10.1002/9781119788010.refs

  • Carroll S and Lin W. (2019). Applied On-Chip Machine Learning for Dynamic Resource Control in Multithreaded Processors. Parallel Processing Letters. 10.1142/S0129626419500130. 29:03. (1950013). Online publication date: 1-Sep-2019.

    https://www.worldscientific.com/doi/abs/10.1142/S0129626419500130

  • Chen M and Mishra P. Assertion-Based Functional Consistency Checking between TLM and RTL Models. Proceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems. (320-325).

    https://doi.org/10.1109/VLSID.2013.208

  • Gerdes M, Kluge F, Ungerer T and Rochange C. The Split-Phase Synchronisation Technique. Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. (88-97).

    https://doi.org/10.1109/RTCSA.2012.11

  • Park C and Park D. (2001). Aggressive superpage support with the shadow memory and the partial-subblock TLB. Microprocessors and Microsystems. 10.1016/S0141-9331(01)00125-9. 25:7. (329-342). Online publication date: 1-Oct-2001.

    http://linkinghub.elsevier.com/retrieve/pii/S0141933101001259

  • Attiya H and Dagan E. (2001). Improved implementations of binary universal operations. Journal of the ACM. 48:5. (1013-1037). Online publication date: 1-Sep-2001.

    https://doi.org/10.1145/502102.502105

  • Yang H, Mertoguno S and Bourbakis N. (2001). Design of the Kydon-RISC processor. Microprocessors and Microsystems. 10.1016/S0141-9331(00)00101-0. 25:1. (1-18). Online publication date: 1-Mar-2001.

    http://linkinghub.elsevier.com/retrieve/pii/S0141933100001010

  • Park C, Chung J, Seong B, Roh Y and Park D. Boosting superpage utilization with the shadow memory and the partial-subblock TLB. Proceedings of the 14th international conference on Supercomputing. (187-195).

    https://doi.org/10.1145/335231.335249

  • Dougan C, Mackerras P and Yodaiken V. Optimizing the idle task and other MMU tricks. Proceedings of the third symposium on Operating systems design and implementation. (229-237).

    /doi/10.5555/296806.296833

  • Rajwar R, Kagi A and Goodman J. Improving the throughput of synchronization by insertion of delays HPCA: 6th International Symposium on High-Performance Computer Architecutre. 10.1109/HPCA.2000.824348. 0-7695-0550-3. (168-179).

    http://ieeexplore.ieee.org/document/824348/

  • Weper R, Zehendner E and Erhard W. (1999). /spl rho/: hierarchical modeling of parallel architectures Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99. 10.1109/EMPDP.1999.746678. 0-7695-0059-5. (233-240).

    http://ieeexplore.ieee.org/document/746678/

  • Omondi A. (1999). Data Flow: Detecting and Resolving Data Hazards. The Microarchitecture of Pipelined and Superscalar Computers. 10.1007/978-1-4757-2989-4_5. (151-184).

    http://link.springer.com/10.1007/978-1-4757-2989-4_5

  • Omondi A. (1999). Control Flow: Branching and Control Hazards. The Microarchitecture of Pipelined and Superscalar Computers. 10.1007/978-1-4757-2989-4_4. (83-150).

    http://link.springer.com/10.1007/978-1-4757-2989-4_4

  • Markatos E, Katevenis M and Vatsolaki P. (1998). The remote enqueue operation on networks of workstations. Network-Based Parallel Computing Communication, Architecture, and Applications. 10.1007/BFb0052203. (1-14).

    http://link.springer.com/10.1007/BFb0052203

  • de Dinechin B. (1998). A unified software pipeline construction scheme for modulo scheduled loops. Languages and Compilers for Parallel Computing. 10.1007/BFb0032706. (382-393).

    http://link.springer.com/10.1007/BFb0032706

  • Moon S and Ebcioğlu K. (1997). Parallelizing nonnumerical code with selective scheduling and software pipelining. ACM Transactions on Programming Languages and Systems. 19:6. (853-898). Online publication date: 1-Nov-1997.

    https://doi.org/10.1145/267959.269966

  • Wang H, Sun T and Yang Q. (1997). Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags. IEEE Transactions on Computers. 46:11. (1187-1201). Online publication date: 1-Nov-1997.

    https://doi.org/10.1109/12.644293

  • Moon S and Ebcioğlu K. Performance analysis of tree VLIW architecture for exploiting branch ILP in non-numerical code. Proceedings of the 11th international conference on Supercomputing. (301-308).

    https://doi.org/10.1145/263580.263653

  • Katevenis M, Markatos E, Kalokerinos G and Dollas A. (1997). Telegraphos. Journal of Parallel and Distributed Computing. 43:2. (94-108). Online publication date: 15-Jun-1997.

    https://doi.org/10.1006/jpdc.1997.1334

  • Markatos E and Katevenis M. User-level DMA without operating system kernel modification Third International Symposium on High-Performance Computer Architecture. 10.1109/HPCA.1997.569696. 0-8186-7764-3. (322-331).

    http://ieeexplore.ieee.org/document/569696/

  • Wilberg J and Camposano R. (1997). VLIW Processor Codesign for Video Processing. Design Automation for Embedded Systems. 2:1. (79-119). Online publication date: 1-Jan-1997.

    https://doi.org/10.1023/A:1008818711786

  • Dupont de Dinechin B. (1997). A unified software pipeline construction scheme for modulo scheduled loops. Parallel Computing Technologies. 10.1007/3-540-63371-5_20. (189-200).

    http://link.springer.com/10.1007/3-540-63371-5_20

  • Páez-Monzón G and Páez-Monzón C. (1996). The RISC processor DMN-6: a unified data-control flow architecture. ACM SIGARCH Computer Architecture News. 24:4. (3-10). Online publication date: 1-Sep-1996.

    https://doi.org/10.1145/235688.235689

  • Hauser J. (1996). Handling floating-point exceptions in numeric programs. ACM Transactions on Programming Languages and Systems. 18:2. (139-174). Online publication date: 1-Mar-1996.

    https://doi.org/10.1145/227699.227701

  • Markatos E and Katevenis M. Telegraphos. Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture.

    /doi/10.5555/525424.822655

  • Engler D, Hsieh W and Kaashoek M. C: a language for high-level, efficient, and machine-independent dynamic code generation. Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages. (131-144).

    https://doi.org/10.1145/237721.237765

  • Guy B and Haggard R. High performance branch prediction 28th Southeastern Symposium on System Theory. 10.1109/SSST.1996.493550. 0-8186-7352-4. (472-476).

    http://ieeexplore.ieee.org/document/493550/

  • Markatos E and Katevenis M. Telegraphos: high-performance networking for parallel processing on workstation clusters Proceedings. Second International Symposium on High-Performance Computer Architecture. 10.1109/HPCA.1996.501181. 0-8186-7237-4. (144-153).

    http://ieeexplore.ieee.org/document/501181/

  • Chun Xia and Torrellas J. Improving the data cache performance of multiprocessor operating systems Proceedings. Second International Symposium on High-Performance Computer Architecture. 10.1109/HPCA.1996.501176. 0-8186-7237-4. (85-94).

    http://ieeexplore.ieee.org/document/501176/

  • Draves S. (1996). Compiler generation for interactive graphics using intermediate code. Partial Evaluation. 10.1007/3-540-61580-6_6. (95-114).

    http://link.springer.com/10.1007/3-540-61580-6_6

  • Engler D, Kaashoek M and O'Toole J. (1995). Exokernel. ACM SIGOPS Operating Systems Review. 29:5. (251-266). Online publication date: 3-Dec-1995.

    https://doi.org/10.1145/224057.224076

  • Talluri M, Hill M and Khalidi Y. (1995). A new page table for 64-bit address spaces. ACM SIGOPS Operating Systems Review. 29:5. (184-200). Online publication date: 3-Dec-1995.

    https://doi.org/10.1145/224057.224071

  • Engler D, Kaashoek M and O'Toole J. Exokernel. Proceedings of the fifteenth ACM symposium on Operating systems principles. (251-266).

    https://doi.org/10.1145/224056.224076

  • Talluri M, Hill M and Khalidi Y. A new page table for 64-bit address spaces. Proceedings of the fifteenth ACM symposium on Operating systems principles. (184-200).

    https://doi.org/10.1145/224056.224071

  • Edmondson J, Rubinfeld P, Preston R and Rajagopalan V. (1995). Superscalar Instruction Execution in the 21164 Alpha Microprocessor. IEEE Micro. 15:2. (33-43). Online publication date: 1-Apr-1995.

    https://doi.org/10.1109/40.372349

  • Mogul J, Bartlett J, Mayo R and Srivastava A. Performance implications of multiple pointer sizes. Proceedings of the USENIX 1995 Technical Conference Proceedings. (16-16).

    /doi/10.5555/1267411.1267427

  • Beaty S and Johnson G. The effect of adding a scalar D-cache to the Cray-4 vector processor 1st International Conference on Algorithms and Architectures for Parallel Processing. 10.1109/ICAPP.1995.472189. 0-7803-2018-2. (227-230).

    http://ieeexplore.ieee.org/document/472189/

  • (1995). References. Scalable Shared-Memory Multiprocessing. 10.1016/B978-1-55860-315-8.50017-8. (317-331).

    https://linkinghub.elsevier.com/retrieve/pii/B9781558603158500178

  • Talluri M and Hill M. (1994). Surpassing the TLB performance of superpages with less operating system support. ACM SIGOPS Operating Systems Review. 28:5. (171-182). Online publication date: 1-Dec-1994.

    https://doi.org/10.1145/381792.195531

  • Talluri M and Hill M. Surpassing the TLB performance of superpages with less operating system support. Proceedings of the sixth international conference on Architectural support for programming languages and operating systems. (171-182).

    https://doi.org/10.1145/195473.195531

  • Talluri M and Hill M. (1994). Surpassing the TLB performance of superpages with less operating system support. ACM SIGPLAN Notices. 29:11. (171-182). Online publication date: 1-Nov-1994.

    https://doi.org/10.1145/195470.195531

  • Tyson G and Farrens M. (1994). Code scheduling for multiple instruction stream architectures. International Journal of Parallel Programming. 22:3. (243-272). Online publication date: 1-Jun-1994.

    https://doi.org/10.1007/BF02577734

  • Kotz D and Crow P. (1994). The expected lifetime of “single-address-space” operating systems. ACM SIGMETRICS Performance Evaluation Review. 22:1. (161-170). Online publication date: 1-May-1994.

    https://doi.org/10.1145/183019.183036

  • Kotz D and Crow P. The expected lifetime of “single-address-space” operating systems. Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems. (161-170).

    https://doi.org/10.1145/183018.183036

  • Farrens M, Tyson G and Pleszkun A. A study of single-chip processor/cache organizations for large numbers of transistors. Proceedings of the 21st annual international symposium on Computer architecture. (338-347).

    https://doi.org/10.1145/191995.192066

  • Farrens M, Tyson G and Pleszkun A. (1994). A study of single-chip processor/cache organizations for large numbers of transistors. ACM SIGARCH Computer Architecture News. 22:2. (338-347). Online publication date: 1-Apr-1994.

    https://doi.org/10.1145/192007.192066

  • Hauser C, Jacobi C, Theimer M, Welch B and Weiser M. Using threads in interactive systems. Proceedings of the fourteenth ACM symposium on Operating systems principles. (94-105).

    https://doi.org/10.1145/168619.168627

  • Farrens M, Tyson G and Pleszkun A. A study of single-chip processor/cache organizations for large numbers of transistors 21 International Symposium on Computer Architecture. 10.1109/ISCA.1994.288137. 0-8186-5510-0. (338-347).

    http://ieeexplore.ieee.org/document/288137/

  • Tyson G and Farrens M. Techniques for extracting instruction level parallelism on MIMD architectures. Proceedings of the 26th annual international symposium on Microarchitecture. (128-137).

    /doi/10.5555/255235.255273

  • Hauser C, Jacobi C, Theimer M, Welch B and Weiser M. (1993). Using threads in interactive systems. ACM SIGOPS Operating Systems Review. 27:5. (94-105). Online publication date: 1-Dec-1993.

    https://doi.org/10.1145/173668.168627

  • Deering S. (1993). SIP. IEEE Network: The Magazine of Global Internetworking. 7:3. (16-28). Online publication date: 1-May-1993.

    https://doi.org/10.1109/65.224022

  • McLellan E. (1993). The Alpha AXP Architecture and 21064 Processor. IEEE Micro. 13:3. (36-47). Online publication date: 1-May-1993.

    https://doi.org/10.1109/40.216747

  • Sites R, Chernoff A, Kirk M, Marks M and Robinson S. (1993). Binary translation. Communications of the ACM. 36:2. (69-81). Online publication date: 1-Feb-1993.

    https://doi.org/10.1145/151220.151227

  • Sites R. (1993). Alpha AXP architecture. Communications of the ACM. 10.1145/151220.151226. 36:2. (33-44). Online publication date: 1-Feb-1993.

    https://dl.acm.org/doi/10.1145/151220.151226

  • Kronenberg N, Benson T, Cardoza W, Jagannathan R and Thomas B. (1993). Porting OpenVMS from VAX to Alpha AXP. Communications of the ACM. 36:2. (45-53). Online publication date: 1-Feb-1993.

    https://doi.org/10.1145/151220.151224

  • Tyson G and Farrens M. (1993). Techniques for extracting instruction level parallelism on MIMD architectures Proceedings of 26th Annual International Symposium on Microarchitecture (Cat. No.93TH0602-3). 10.1109/MICRO.1993.282749. 0-8186-5280-2. (128-137).

    http://ieeexplore.ieee.org/document/282749/