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- research-articleMarch 2025JUST ACCEPTED
An Efficient Delta Compression Framework Seamlessly Integrated into Inline Deduplication
Delta compression can complement data deduplication by further minimizing redundancy through the compression of non-duplicate data chunks. When adding delta compression to deduplication-based backup systems, however, two primary challenges arise that ...
- posterDecember 2024
Emotionally Guided Symbolic Music Generation Using Diffusion Models: The AGE-DM Approach
MMAsia '24: Proceedings of the 6th ACM International Conference on Multimedia in AsiaArticle No.: 127, Pages 1–5https://doi.org/10.1145/3696409.3700289Music’s profound impact on emotions and mood has prompted growing interest in developing AI models capable of generating music that aligns with specific emotional intents. However, existing methods, such as those utilizing modified LSTM networks or GANs, ...
- research-articleNovember 2024
A boosting framework for positive-unlabeled learning
AbstractPositive-unlabeled (PU) learning deals with binary classification problems where only positive and unlabeled data are available. In this paper, we introduce a novel boosting framework, Adaptive PU (AdaPU), for learning from PU data. AdaPU builds ...
- research-articleOctober 2024
Self-supervised visual–textual prompt learning for few-shot grading of gastric intestinal metaplasia
AbstractGastric intestinal metaplasia (GIM) is a frequent lesion of the gastrointestinal tract, and its clinical grading can significantly reduce the risk of gastric cancer. Pre-trained vision–language models have demonstrated impressive generalizability ...
- research-articleSeptember 2024
Skyway: Accelerate Graph Applications with a Dual-Path Architecture and Fine-Grained Data Management
Journal of Computer Science and Technology (JCST), Volume 39, Issue 4Pages 871–894https://doi.org/10.1007/s11390-023-2939-xAbstractGraph processing is a vital component of many AI and big data applications. However, due to its poor locality and complex data access patterns, graph processing is also a known performance killer of AI and big data applications. In this work, we ...
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- research-articleNovember 2024
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption
- Jianan Mu,
- Husheng Han,
- Shangyi Shi,
- Jing Ye,
- Zizhen Liu,
- Shengwen Liang,
- Meng Li,
- Mingzhe Zhang,
- Song Bian,
- Xing Hu,
- Huaiwei Li,
- Xiaowei Li
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation ConferenceArticle No.: 26, Pages 1–6https://doi.org/10.1145/3649329.3657331The use of cross-scheme fully homomorphic encryption (FHE) in privacy-preserving applications present to be a new challenge to hardware accelerator design. Existing accelerator architectures with customized polynomial-level operator abstraction fail to ...
- research-articleJune 2024
A Swin transformer encoder-based StyleGAN for unbalanced endoscopic image enhancement
Computers in Biology and Medicine (CBIM), Volume 175, Issue Chttps://doi.org/10.1016/j.compbiomed.2024.108472AbstractWith the rapid development of artificial intelligence, automated endoscopy-assisted diagnostic systems have become an effective tool for reducing the diagnostic costs and shortening the treatment cycle of patients. Typically, the performance of ...
Highlights- The proposed STE-StyleGAN model implements image-to-image compilation and generates high-resolution endoscopic images.
- Swin transformer hierarchically encodes images and self-attention strengthens the connections between different ...
- research-articleApril 2024
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPages 199–210https://doi.org/10.1145/3626202.3637566This paper aims at high and portable performance for tensor computations across spatial (e.g., FPGAs) and vector architectures (e.g., GPUs). The state-of-the-art usually address performance portability across vector architectures (CPUs and GPUs). However,...
- ArticleMay 2023
Words Can Be Confusing: Stereotype Bias Removal in Text Classification at the Word Level
Advances in Knowledge Discovery and Data MiningPages 99–111https://doi.org/10.1007/978-3-031-33383-5_8AbstractText classification is a widely used task in natural language processing. However, the presence of stereotype bias in text classification can lead to unfair and inaccurate predictions. Stereotype bias is particularly prevalent in words that are ...
- ArticleNovember 2022
ESTD: Empathy Style Transformer with Discriminative Mechanism
AbstractLanguage expressions without empathy can neither effectively convey the expresser’s concern and goodwill, but also have a negative effect on the emotional and mental health of the recipients of the information. Compared to harsh or aggressive ...
- research-articleOctober 2021
Distilling Bit-level Sparsity Parallelism for General Purpose Deep Learning Acceleration
MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on MicroarchitecturePages 963–976https://doi.org/10.1145/3466752.3480123Along with the rapid evolution of deep neural networks, the ever-increasing complexity imposes formidable computation intensity to the hardware accelerator. In this paper, we propose a novel computing philosophy called “bit interleaving” and the ...
- research-articleMarch 2022
ECG Prediction based on Bidirectional Time Series Chain Discovery Algorithm
ICCSE '21: 5th International Conference on Crowd Science and EngineeringPages 95–102https://doi.org/10.1145/3503181.3503197Time series chains are a set of subsequence patterns arranged in chronological order, such that each pattern is similar to the one before it, but the first and last patterns can be arbitrarily different. At present, time series chain discovery ...
- research-articleOctober 2021
BitX: Empower Versatile Inference with Hardware Runtime Pruning
ICPP '21: Proceedings of the 50th International Conference on Parallel ProcessingArticle No.: 15, Pages 1–12https://doi.org/10.1145/3472456.3472513Classic DNN pruning mostly leverages software-based methodologies to tackle the accuracy/speed tradeoff, which involves complicated procedures like critical parameter searching, fine-tuning and sparse training to find the best plan. In this paper, we ...
- research-articleSeptember 2021
CoPIM: a concurrency-aware PIM workload offloading architecture for graph applications
ISLPED '21: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and DesignArticle No.: 33, Pages 1–6https://doi.org/10.1109/ISLPED52811.2021.9502483Processing-in-Memory (PIM) is considered a promising solution to improve the performance of graph-computing applications by minimizing the data movement between the host and memory. Which workload to offload and how to offload it to PIM logic determine ...
- research-articleNovember 2024
FindeR: Accelerating FM-Index-based Exact Pattern Matching in Genomic Sequences through ReRAM technology
PACT '19: Proceedings of the International Conference on Parallel Architectures and Compilation TechniquesPages 283–294https://doi.org/10.1109/PACT.2019.00030Genomics is the critical key to enabling precision medicine, ensuring global food security and enforcing wildlife conservation. The massive genomic data produced by various genome sequencing technologies presents a significant challenge for genome ...
- research-articleSeptember 2019
Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM
IEEE Transactions on Computers (ITCO), Volume 68, Issue 9Pages 1365–1375https://doi.org/10.1109/TC.2019.2900036MLC PCM provides high-density data storage and extended data retention; therefore it is a promising alternative for DRAM main memory. However, its low write performance is a major obstacle to commercialization. One opportunity for improving the latency of ...
- research-articleJune 2019
Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019Article No.: 115, Pages 1–6https://doi.org/10.1145/3316781.33178583D vertical ReRAM (3DV-ReRAM) emerges as one of the most promising alternatives to DRAM due to its good scalability beyond 10nm. Monolithic 3D (M3D) integration enables 3DV-ReRAM to improve its array area efficiency by stacking peripheral circuits ...
- research-articleMarch 2018
SIMPO: A Scalable In-Memory Persistent Object Framework Using NVRAM for Reliable Big Data Computing
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 1Article No.: 7, Pages 1–28https://doi.org/10.1145/3167972While CPU architectures are incorporating many more cores to meet ever-bigger workloads, advance in fault-tolerance support is indispensable for sustaining system performance under reliability constraints. Emerging non-volatile memory technologies are ...
- research-articleJune 2017
Scalable Adaptive NUMA-Aware Lock
IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume 28, Issue 6Pages 1754–1769https://doi.org/10.1109/TPDS.2016.2630695Scalable locking is a key building block for scalable multi-threaded software. Its performance is especially critical in multi-socket, multi-core machines with non-uniform memory access (NUMA). Previous schemes such as in-place locks and delegation ...
- research-articleFebruary 2016
Scalable adaptive NUMA-aware lock: combining local locking and remote locking for efficient concurrency
PPoPP '16: Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel ProgrammingArticle No.: 50, Pages 1–2https://doi.org/10.1145/2851141.2851176Scalable locking is a key building block for scalable multi-threaded software. Its performance is especially critical in multi-socket, multi-core machines with non-uniform memory access (NUMA). Previous schemes such as local locking and remote locking ...
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ACM SIGPLAN Notices: Volume 51 Issue 8