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Predicting Future-System Reliability with a Component-Level DRAM Fault Model
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitecturePages 944–956https://doi.org/10.1145/3613424.3614294We introduce a new fault model for recent and future DRAM systems that uses empirical analysis to derive DRAM internal-component level fault models. This modeling level offers higher fidelity and greater predictive capability than prior models that rely ...
- research-articleNovember 2021
Accelerating bandwidth-bound deep learning inference with main-memory accelerators
SC '21: Proceedings of the International Conference for High Performance Computing, Networking, Storage and AnalysisArticle No.: 44, Pages 1–14https://doi.org/10.1145/3458817.3476146Matrix-matrix multiplication operations (GEMMs) are important in many HPC and machine-learning applications. They are often mapped to discrete accelerators (e.g., GPUs) to improve performance. However, we find that large tall/skinny and fat/short ...