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- research-articleJune 2023
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses
- Rakesh Nadig,
- Mohammad Sadrosadati,
- Haiyu Mao,
- Nika Mansouri Ghiasi,
- Arash Tavakkol,
- Jisung Park,
- Hamid Sarbazi-Azad,
- Juan Gómez Luna,
- Onur Mutlu
ISCA '23: Proceedings of the 50th Annual International Symposium on Computer ArchitectureArticle No.: 36, Pages 1–16https://doi.org/10.1145/3579371.3589071The performance and capacity of solid-state drives (SSDs) are continuously improving to meet the increasing demands of modern data-intensive applications. Unfortunately, communication between the SSD controller and memory chips (e.g., 2D/3D NAND flash ...
- research-articleJune 2022
SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-sequence mapping
- Damla Senol Cali,
- Konstantinos Kanellopoulos,
- Joël Lindegger,
- Zülal Bingöl,
- Gurpreet S. Kalsi,
- Ziyi Zuo,
- Can Firtina,
- Meryem Banu Cavlak,
- Jeremie Kim,
- Nika Mansouri Ghiasi,
- Gagandeep Singh,
- Juan Gómez-Luna,
- Nour Almadhoun Alserr,
- Mohammed Alser,
- Sreenivas Subramoney,
- Can Alkan,
- Saugata Ghose,
- Onur Mutlu
ISCA '22: Proceedings of the 49th Annual International Symposium on Computer ArchitecturePages 638–655https://doi.org/10.1145/3470496.3527436A critical step of genome sequence analysis is the mapping of sequenced DNA fragments (i.e., reads) collected from an individual to a known linear reference genome sequence (i.e., sequence-to-sequence mapping). Recent works replace the linear reference ...
- ArticleApril 2021
SIMDRAM: a framework for bit-serial SIMD processing using DRAM
- Nastaran Hajinazar,
- Geraldo F. Oliveira,
- Sven Gregorio,
- João Dinis Ferreira,
- Nika Mansouri Ghiasi,
- Minesh Patel,
- Mohammed Alser,
- Saugata Ghose,
- Juan Gómez-Luna,
- Onur Mutlu
ASPLOS '21: Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating SystemsPages 329–345https://doi.org/10.1145/3445814.3446749Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable full adoption of processing-using-DRAM, it is necessary to provide support for more complex operations. In this ...
- research-articleOctober 2019
SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations
- Konstantinos Kanellopoulos,
- Nandita Vijaykumar,
- Christina Giannoula,
- Roknoddin Azizi,
- Skanda Koppula,
- Nika Mansouri Ghiasi,
- Taha Shahroodi,
- Juan Gomez Luna,
- Onur Mutlu
MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on MicroarchitecturePages 600–614https://doi.org/10.1145/3352460.3358286Important workloads, such as machine learning and graph analytics applications, heavily involve sparse linear algebra operations. These operations use sparse matrix compression as an effective means to avoid storing zeros and performing unnecessary ...
- research-articleJune 2019
CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability
- Hasan Hassan,
- Minesh Patel,
- Jeremie S. Kim,
- A. Giray Yaglikci,
- Nandita Vijaykumar,
- Nika Mansouri Ghiasi,
- Saugata Ghose,
- Onur Mutlu
ISCA '19: Proceedings of the 46th International Symposium on Computer ArchitecturePages 129–142https://doi.org/10.1145/3307650.3322231DRAM has been the dominant technology for architecting main memory for decades. Recent trends in multi-core system design and large-dataset applications have amplified the role of DRAM as a critical system bottleneck. We propose Copy-Row DRAM (CROW), a ...
- research-articleOctober 2018
Reducing DRAM latency via charge-level-aware look-ahead partial restoration
- Yaohua Wang,
- Arash Tavakkol,
- Lois Orosa,
- Saugata Ghose,
- Nika Mansouri Ghiasi,
- Minesh Patel,
- Jeremie S. Kim,
- Hasan Hassan,
- Mohammad Sadrosadati,
- Onur Mutlu
MICRO-51: Proceedings of the 51st Annual IEEE/ACM International Symposium on MicroarchitecturePages 298–311https://doi.org/10.1109/MICRO.2018.00032Long DRAM access latency is a major bottleneck for system performance. In order to access data in DRAM, a memory controller (1) activates (i.e., opens) a row of DRAM cells in a cell array, (2) restores the charge in the activated cells back to their ...
- research-articleJune 2018
FLIN: enabling fairness and enhancing performance in modern NVMe solid state drives
- Arash Tavakkol,
- Mohammad Sadrosadati,
- Saugata Ghose,
- Jeremie S. Kim,
- Yixin Luo,
- Yaohua Wang,
- Nika Mansouri Ghiasi,
- Lois Orosa,
- Juan Gómez-Luna,
- Onur Mutlu
ISCA '18: Proceedings of the 45th Annual International Symposium on Computer ArchitecturePages 397–410https://doi.org/10.1109/ISCA.2018.00041Modern solid-state drives (SSDs) use new host-interface protocols, such as NVMe, to provide applications with fast access to storage. These new protocols make use of a concept known as the multi-queue SSD (MQ-SSD), where the SSD has direct access to the ...