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- research-articleJuly 2008
Logic Minimization and Testability of 2-SPP Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 27, Issue 7Pages 1190–1202https://doi.org/10.1109/TCAD.2008.923072The 2-SPP networks are three-level EXOR-AND-OR forms, with EXOR gates being restricted to fan-in 2. This paper presents a heuristic algorithm for the synthesis of these networks in a form that is fully testable in the stuck-at fault model (SAFM). The ...
- research-articleNovember 2006
Effect of improved lower bounds in dynamic BDD reordering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 25, Issue 5Pages 902–909https://doi.org/10.1109/TCAD.2005.854632In this paper, we present new lower bounds on binary decision diagram (BDD) size. These lower bounds are derived from more general lower bounds that recently were given in the context of exact BDD minimization. The results presented in this paper are ...
- research-articleNovember 2006
Combining ordered best-first search with branch and bound for exact BDD minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 24, Issue 10Pages 1515–1529https://doi.org/10.1109/TCAD.2005.852053Reduced-ordered binary decision diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis. The size of BDDs depends on a chosen variable ordering, i.e., the size ...
- research-articleNovember 2006
An improved branch and bound algorithm for exact BDD minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 22, Issue 12Pages 1657–1663https://doi.org/10.1109/TCAD.2003.819427Ordered binary decision diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of the BDDs depends on a chosen variable ...
- research-articleNovember 2006
Using lower bounds during dynamic BDD minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 20, Issue 1Pages 51–57https://doi.org/10.1109/43.905674Ordered binary decision diagrams (BDDs) are a data structure for the representation and manipulation of Boolean functions, often applied in very large scale integration (VLSI) computer-aided design (CAD). The choice of variable ordering largely ...
- research-articleNovember 2006
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 19, Issue 3Pages 384–389https://doi.org/10.1109/43.833206We present a new exact algorithm for finding the optimal variable ordering for reduced ordered binary decision diagrams (BDD's). The algorithm makes use of a lower bound technique known from very large scale integration design. Up to now this technique ...
- research-articleNovember 2006
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 18, Issue 2Pages 81–100https://doi.org/10.1109/43.743706In this paper we study the effect of using information about (partial) symmetries for the minimization of reduced ordered binary decision diagrams (ROBDD's). The influence of symmetries for the integration in dynamic variable ordering is studied for ...
- research-articleNovember 2006
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 17, Issue 10Pages 965–973https://doi.org/10.1109/43.728917Ordered Kronecker functional decision diagrams (OKFDD's) are a data structure for efficient representation and manipulation of Boolean functions. OKFDD's are a generalization of ordered binary decision diagrams (OBDD)s) and ordered functional decision ...
- research-articleNovember 2006
The complexity of the inclusion operation on OFDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 17, Issue 5Pages 457–459https://doi.org/10.1109/43.703943Ordered functional decision diagrams (OFDD's) are a data structure for representation and manipulation of Boolean functions. A polynomial time algorithm for the test whether f⩽g for functions f and g given by OFDD's is presented. This is the last ...
- research-articleNovember 2006
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 16, Issue 1Pages 1–5https://doi.org/10.1109/43.559327In this paper, a polynomial time algorithm for the minimization of fixed polarity Reed-Muller expressions (FPRMs) for totally symmetric functions based on ordered functional decision diagrams (OFDDs) is presented. A generalization to partially symmetric ...
- research-articleNovember 2006
On the generation of area-time optimal testable adders
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 14, Issue 9Pages 1049–1066https://doi.org/10.1109/43.406707We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn, and the fault model FM. FM may in particular be chosen as ...
- research-articleOctober 2006
Testability of SPP Three-Level Logic Networks in Static Fault Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 25, Issue 10Pages 2241–2248https://doi.org/10.1109/TCAD.2005.862746Full testability is a desirable property for a minimal logic network. The classical minimal two-level sum of products (SOP) networks are fully testable in some standard fault models. In this paper, the authors investigate the testability of recently ...
- research-articleJune 2003
Exact routing with search space reduction
IEEE Transactions on Computers (ITCO), Volume 52, Issue 6Pages 815–825https://doi.org/10.1109/TC.2003.1204836The layout problem in VLSI-design can be broken up into the subtasks partitioning, floorplanning, placement, and routing. In the routing phase, a large number of connections between the blocks and cells have to be established, while intersections lead ...
- ArticleSeptember 2001
Minimization of OPKFDDs Using Genetic Algorithms
Abstract: OPKFDDs (Ordered Pseudo-Kronecker Functional Decision Diagrams) are one of ordered-DDs (Decision Diagrams) in which each node can take one of three decomposition types: Shannon, positive Davio and negative Davio. OPKFDDs provide ...
- ArticleSeptember 2001
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement
Abstract: In various areas of computer science and mathematics, including scientific computing, task scheduling and VLSI design, the graph concept is use d for modeling purposes, and graph partitioning algorithms are required to obtain solutions. E.g., ...
- research-articleSeptember 1999
- ArticleJanuary 1997
Pseudo Kronecker Expressions for Symmetric Functions
Pseudo Kronecker Expressions (PSDKROs) are a class of AND/EXOR expressions. In this paper it is proven that exact minimization of PSDKROs for totally symmetric functions can be performed in polynomial time. A new implementation method for PSDKROs is ...
- ArticleJanuary 1996
Verification of multi-valued logic networks
A method for verification of Multi-Valued Logic Networks (MVLNs) using Ordered Multi-Valued Decision Diagrams (OMDDs) is presented. For tree-like MVLNs an upper bound on the OMDD size can be proven. Thus, heuristics known for OBDDs can also be used for ...