Complexity adaptive iterative receiver performing TBICM-ID-SSD

Flexible and iterative baseband receivers with advanced channel codes like turbo codes are widely adopted nowadays, ensuring promising error rate performances. Extension of this principle with an additional iterative feedback loop to the demapping function has proven to provide substantial error performance gain at the cost of increased complexity. However, this complexity overhead constitutes commonly an obstacle for its consideration in real implementations. This article illustrates the opposite of what is commonly assumed and proposes a complexity adaptive iterative receiver performing iterative demapping with turbo decoding (TBICM-ID-SSD). Targeting identical error rate, the article shows that for certain system configurations TBICM-ID-SSD presents lower complexity than TBICM-SSD (without iterative demapping). This original result is obtained when considering the equivalent number of iterations through detailed analysis of the corresponding computational and memory access complexity. The analysis is conducted for different parameters in terms of modulation orders and code rates and independently from the architecture for a fair comparison. Considering the proposed adaptive receiver which is able to perform both TBICM-ID-SSD and TBICM-SSD modes, results demonstrate a reduced complexity with TBICM-SSD for high modulation orders. However, for low modulation orders as for QPSK, results show a reduction in arithmetic operations and read access memory up to 45.9% and 47%, respectively for using the TBICM-ID-SSD mode rather than TBICM-SSD performing six turbo decoding iterations over Rayleigh fading channel with erasures.

Advanced wireless communication standards impose the use of modern techniques to improve spectral efficiency and reliability. Among these techniques, bit-interleaved coded modulation (BICM) [1] with different modulation orders and Turbo Codes with various code rates are frequently adopted.

The BICM principle currently represents the state-of-the-art in coded modulations over fading channels. The BICM with iterative demapping (BICM-ID) scheme proposed in [2] is based on BICM with additional soft feedback from the soft-input soft-output (SISO) convolutional decoder to the constellation demapper. In [3], the convolutional code classically used in BICM-ID schemes was replaced by a turbo code. Only a small gain of 0.1 dB was observed. This result makes BICM-ID with turbo-like coding solutions (TBICM-ID) unsatisfactory with respect to the added decoding complexity.

On the other hand, signal space diversity (SSD) technique, which consists of a rotation of the constellation followed by a signal space component interleaving, has been recently proposed [4, 5]. It increases the diversity order of a communication system without using extra bandwidth.

Combining SSD technique with TBICM-ID at the receiver side has shown excellent error rate performance results particularly in severe channel conditions (erasure, multi-path, real fading models) [6, 7]. These results were behind the adoption of this system in DVB-T2 standard (using LDPC channel code). These results will also lead for further adoption discussions in the upcoming standards using turbo codes [6]. The TBICM and TBICM-ID modes applying the SSD technique are denoted by TBICM-SSD and TBICM-ID-SSD.

In fact, almost all related works using these techniques have focused only on error rate performance without considering the implementation perspective. This is due mainly to the commonly assumed impact in terms of complexity overhead. In this article, we demonstrate the effectiveness of the iterative demapping even in terms of complexity for certain system configurations (modulation orders and code rates). In this context, a novel complexity adaptive iterative receiver, performing either in TBICM-ID-SSD mode or in TBICM-SSD mode, is proposed. This original proposal is based on a thorough analysis of the corresponding computational and memory access complexity.

It is worth to note that the article does not provide a comparison in terms of area, as one iterative receiver is considered to perform both modes (TBICM-ID-SSD and TBICM-SSD).

The rest of the article is organized as follows. Section System model and algorithms presents the system model with the associated parameters and gives a brief description of the underlined algorithms for iterative demapping and turbo decoding. Section Complexity evaluation and normalization presents an evaluation of the receiver complexity in terms of number and type of arithmetic operations and memory access. Section Number of iterations analysis for identical complexity analyzes the number of TBCIM-SSD and TBCIM-ID-SSD iterations for identical complexity. Section Complexity analysis for identical performance shows a complexity analysis for identical TBCIM-SSD and TBCIM-ID-SSD error rate performances. Finally, Section Conclusion concludes the article.

This section describes the system model and the considered parameters of the transmitter, channel, and receiver of Figure 1. In addition, it gives a brief presentation of the underlined algorithms for the iterative demapping and decoding.

The system model of the transmitter, channel, and TBICM-ID-SSD receiver.

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System model

On the transmitter side, information bits U which are called systematic bits are regrouped into symbols u _i consisting of q bits, and encoded with an q-binary turbo encoder. It consists of a parallel concatenation of two identical convolutional codes (PCCC). The output codeword C is then punctured to reach a desired coding rate R _c . We consider in this work the 8-state double binary (q=2) [8] turbo code adopted in the WiMax standard.

In order to gain resilience against error bursts, the resulting sequence is interleaved using an S-random interleaver π₂ with $S=\sqrt{N/4}$. Punctured and interleaved bits denoted by v _i are then gray mapped to complex channel symbols s _q chosen from a 2^M-ary constellation X, where M is the number of bits per modulated symbol.

Applying the SSD consists first of the rotation of the mapped symbols s _q . The resulting rotated symbols are denoted as s_r,q. The performance gain obtained when using a rotated constellation X _r depends on the choice of the rotation angle. The optimum rotation angle depends on the chosen modulation and channel type. In this regard, a thorough analysis has been done for the 2nd-generation terrestrial transmission system developed by the DVB Project (DVB-T2) which adopted the rotated constellation technique. A single rotation angle [7] has been chosen for each constellation size independently of the channel type. These angle values are presented in Table 1 and are adopted in this work.

The second step when applying SSD at the transmitter consists of signal space component interleaving. A simple delay is introduced between the transmission of I and Q components. Mapped and shifted symbols $s_{r,q}^{″}$are then transmitted over a noisy and Rayleigh fast fading channel with or without erasure. The erasure channel model has been used in the case of the DVB-T2 standard to model the destructive interferences caused by the existence of a single-frequency network (SFN). Each received symbol $x_{r,q}^{″}$is affected by a different fading coefficient, an erasure coefficient, and an additive Gaussian noise.

The channel model considered is a frequency non-selective memoryless channel with erasure probability. The received discrete time baseband complex signal can be written as:

where h _q is the Rayleigh fast fading coefficient, ρ _q is the erasure coefficient probability taking value 0 with a probability P _ρ and value 1 with a probability of 1−P _ρ . n _q is a complex white Gaussian noise with spectral density N₀/2 in each component axes, and $h_q^{″}$is the channel attenuation.

Max-log-map demapping algorithm

At the receiver side, the complex received symbols $x_{r,q}^{″}$have their Q-components re-shifted resulting in x_r,q. An extrinsic log-likelihood ratio L_ext,Dem(c_k,q/x_r,q) is calculated for each bit c_k,qcorresponding to the k th bit of the received rotated and modulated symbol x_r,q. After de-interleaving, de-puncturing and turbo decoding, extrinsic information from the turbo decoder L_ext,Dec(c_k,q) is passed through the interleaver, punctured and fed back as a priori information L_apr,Dem(c_k,q) to the demapper in a turbo demapping scheme. The extrinsic information L_ext,Dem(c_k,q/x_r,q) is the difference between the soft output a posteriori L_Dem(c_k,q/x_r,q) and the soft input a priori L_apr,Dem(c_k,q) at the demapper side. It was originally computed in [9] and given by the expression below:

Z_l(l=0,1) can be expressed as:

where $X_{r,l}^k$, with l∈{0,1}, are the symbol sets of the constellation for which symbols have their k th bit equal to l. P(c_i,q) is the probability of the i th bit of constellation symbol s_r,q computed through a priori information L_apr,Dem(c_k,q). Reducing the complexity of the expressions above can be performed by applying the max-log approximation. Thus, Equation (2) can be written as [9]:

where

and

All demapping equations are valid for erasure and no erasure channel. In fact, the channel coefficient $h_q^{″}$will take into consideration the erasure coefficient given by the channel detector. These simplified expressions exhibit three main computation steps: (a) Euclidean distance computation referred by A _q , (b) a priori adder referred by B_k,q, and (c) minimum finder referred by the min operation of Equation (4).

Max-log-MAP decoding algorithm

Following the demapping function at the receiver side, the turbo decoding is applied. The max-log-MAP algorithm [10] is considered for the SISO convolutional decoders. Using input symbols and a priori decoding information, each SISO decoder computes extrinsic information. The SISO decoder computes first the branch metrics γ _k . Then it computes the forward α _k and backward β _k metrics between two trellis states s and s^″. Max-log-MAP decoding equations, originally proposed in [10], are expressed as follows:

where

Finally the soft output so(d _k =i) and extrinsic information z(d _k =i) of the k th coded symbol are computed [10]:

where SF is the constant scale factor for the Max-Log-MAP decoding algorithm.

In case of iterative demapping and only by one SISO decoder, the bit-level extrinsic information of systematic symbols d _k =c _p c_{p + 1}are computed using (12) and (13). Similar computations are needed for parity symbols c_{p + 2}c_{p + 3}.

These expressions exhibit three main computation steps: (a) branch metrics computation referred by γ _k , (b) state metrics computation referred by (α _k and β _k ), and (c) extrinsic information computation referred by L_apr,Dem and z.

In order to appreciate the complexity of the two iterative modes, an accurate evaluation of the complexity in terms of number and type of operations and memory accesses is required. In this section, we consider the two main blocks of the TBICM-SSD and TBICM-ID-SSD system configurations which are the SISO demapper and the SISO decoder. The proposed evaluation considers the low complexity algorithms presented in Section System model and algorithms.

This evaluation will be presented independently from the architecture (serial, or shuffle, or parallel architecture). It will be based on counting operations without quoting prior SISO demapper and decoder implementation results. A typical fixed-point representation of channel inputs and various metrics is considered. Table 2 summarizes the total number of required quantization bits for each parameter.

Complexity evaluation of SISO demapper

The complexity of SISO demapping depends on the modulation order (in the context of the above fixed parameters). In fact, for each received modulated symbol x_r,q composed of M coded bits, 2^MEuclidean distances are computed. With iterative demapping, a priori information coming from the decoder should be added to the associated Euclidean distance. The minimum distance finder is then applied to search for the closest symbol between the 2^Mconstellation symbols. Thus, the SISO demapper complexity is composed of three principal units: Euclidean distance, a priori adder, and minimum finder functions. For each of these functions we will now consider the equations of Section Max-log-map demapping algorithm (1) the required number and type of arithmetic computations and (2) the required number of read memory access (load) and write memory access (store). The result of this evaluation is summarized in Table 3 and explained below. We use the following notation operation(NbOfBitsOfOperand1,NbOfBitsOfOperand2) for arithmetic operations, and load(NbOfBits)/store(NbOfBits) for read/write memory operations. Thus, add(8,10) indicates an addition operation of two operands; one quantized on 8 bits and the second on 10 bits. Similarly, load(8) indicates a read access memory of 8-bit word length.

1. (1)

   Euclidean distance computation

   For each modulated symbol (input of the demapper):

   • One load(8) to access the fading channel coefficient normalized by the channel variance $\frac{h_q^{″}}{\sigma }$

   • Two load(10) to access the channel symbols $x_{r,q}^I$ and $x_{r,q}^Q$.

   • For each one of the 2^Msymbols of the constellation ($s_{r,j}^I$, $s_{r,j}^Q$):

     • Two load(8) to access the constellation symbols $s_{r,j}^I$ and $s_{r,j}^Q$

     • Two Sub(8,10) to compute ($x_{r,q}^I-s_{r,j}^I$) and ($x_{r,q}^Q-s_{r,j}^Q$)

     • Two Mul(8,10) to multiply with the channel coefficients $\frac{h_q^{″}}{\sigma }$ and $\frac{h_{q-1}^{″}}{\sigma }$

     • Two Mul(18,18) to compute the square of the results above

     • One Add(18,18) to realize the sum of the two Euclidean distance terms

2. (2)

   A priori adder

   For each modulated symbol (input of the demapper):

   • M load(8) to access the a priori information L_apr,Dem(c_i,q)

   • For each one of the 2^Msymbols of the constellation ($s_{r,j}^I$, $s_{r,j}^Q$), except two symbols corresponding to all zeros and all ones:

     • One load(M) to access constellation symbol bits c_i,q. i=0,1,…,M−1

     • One addition of M a priori information to compute $\sum _{i=0,c_{i,q}=1}^{M-1}{L}_{\mathrm{apr},\mathrm{Dem}}\left(c_{i,q}\right)$ of Equation (6). L_apr,Dem(c_i,q) are quantized on 8 bits as shown in Table 2. This addition of M operands is equivalent to the sum of the following 2-input addition operations:

       1. *

          $E\left[\frac{M-1}{2}\right]$ Add(8,8) to realize the sum of the couples of L_apr,Dem(c_i,q). Results are quantized on 9 bits.

          $E\left[\frac{M-1}{4}\right]$

       2. *

          Add(9,9) to realize the sum of the couples of the results above. Results are quantized on 10 bits.

       3. *

          $E\left[\frac{M-1}{8}\right]$ Add(10,10) to realize the final 2-input addition of the results above. Note that $E\left[\frac{M-1}{8}\right]$ equals 0 except for QAM64 and QAM256 where it is equal to 1. The result is quantized on 11 bits.E[x] represents here the ordinary rounding of the positive number x to the nearest integer. Taking the example of QAM16 (M=4), $E\left[\frac{M-1}{2}\right]$=2, $E\left[\frac{M-1}{4}\right]$=1, $E\left[\frac{M-1}{8}\right]$=0.

     • M Sub(8,11) to subtract the LLR of the specific k th bit and thus obtain B_k,q

     • M Sub(11,19) to realize A _q − B_k,q

   However, for the simple QPSK modulation the above operations can be simplified as only two LLRs exist for one modulated symbol. In fact, in Equation (6) there is no need to execute an addition followed by a subtraction of the same LLR. Thus, the total number of required arithmetic operations in this case is 4 Sub(11,19).

3. (3)

   Minimum finder

   For each one of the M bits per modulated symbol:

   • 2^MSub(19,19) to realize the two min operations of Equation (4)

   • One Sub(8,8) to subtract the above found two minimum values

   • One store(8) to store the extrinsic information value

Complexity evaluation of SISO decoder

The SISO decoder complexity is composed of three principal units: branch metric, state metric, and extrinsic information functions. As for the SISO demapper, the result of the complexity evaluation is summarized in Table 3 and explained below. As stated before, the considered turbo code is an 8-state double binary one. At the turbo decoder side, each double binary symbol should be decoded to take a decision over the four possible values (00,01,10,11).

1. (1)

   Branch metrics (γ)

   For each coded symbol (input of the decoder):

   • 4 load(5) to access systematic and parity LLRs

   • 3 load(10) to access demapper normalized extrinsic informations

   • 2 Add(5,5) and 2 Sub(5,5) to compute systematic and parity branch metrics ${\gamma }_{11}^{\mathrm{Sys}}$, ${\gamma }_{10}^{\mathrm{Sys}}$, ${\gamma }_{11}^{\mathrm{Parity}}$ and ${\gamma }_{10}^{\mathrm{Parity}}$

   • 19 Add(5,10) to compute branch metrics γ _k and ${\gamma }_k^{\mathrm{Sys}}+{\gamma }_k^{\mathrm{Parity}}$

   Operations above should be multiplied by 2 to generate forward and backward branch metrics.

2. (2)

   State metrics (α,β)

   For each coded symbol (input of the decoder):

   • 32 Add(10,10) to compute ${\alpha }_{k-1}\left(s^{{}^{″}}\right)+{\gamma }_k(s^{{}^{″}},s)$ for the 32 trellis transitions (8-state double binary trellis)

   • 24 Sub(9,9) to realize the 8 max (4-input) operations of Equation (7). In fact, finding the maximum of N values can be implemented as N-1 max (2-input) operations

   • 8 store(10) to store computed state metrics only for left butterfly algorithm

   Operations above should be multiplied by 2 to generate forward α and backward β state metrics.

3. (3)

   Extrinsic information ( z )

   For each coded symbol (input of the decoder):

   • 8 load(10) to access state metric values

   • 32 Add(10,10) to compute the second required addition operation in Equation (10) for the 32 trellis transitions

   • 28 Sub(9,9) to realize the 4 max (8-input) operations of Equation (10)

   • 4 Sub(10,10) to subtract symbol-level intrinsic information from the computed soft value (generating symbol-level extrinsic information)

   • 8 Sub(9,9) and 4 Sub(10,10) to realize the 8 max (2-input) operations and compute 4 bit-level (systematic and parity) extrinsic information as demapper a priori information (Equations (12) and (13)). This computation is done only for one of the two SISO decoders

   • 4 store(10) to store the computed bit-level (systematic and parity) extrinsic information

   • 3 Sub(10,10) to normalize symbol-level extrinsic information by subtracting the one related to decision 00

   • 3 Mul(4,10) to multiply the symbol-level extrinsic information by a scaling factor SF

   • 3 store(10) to store the computed DEC ₁ symbol-level extrinsic information as DEC ₂ a priori symbol-level information

Complexity normalization

A fair comparison between the two modes (TBICM-SSD and TBICM-ID-SSD) requires arithmetic and memory access operations normalization. For arithmetic operations, normalization has been done in terms of 2-input one bit full adders (Add(1,1)). Each one of the adders, subtractors, and multipliers can be converted into equivalent number of Add(1,1). For adders and subtractors, bit-to-bit half and full adders are used and generalized for operand sizes n₁ and n₂. Obtained formulas are summarized in Table 4 with simple, yet accurate, analysis of all corner cases. Similarly, multiplication operations are normalized using successive addition operations. Memory access operation of m word of size n are normalized to one memory access operation of m×n bits.

Applying the proposed complexity normalization approach to Table 3 leads to the results shown in Table 5. This table summarizes the number of normalized operations required to process one modulated and one coded symbol per iteration for all the functional units of the SISO demapper and SISO decoder. Using this table, it becomes possible to compare the complexity of these heterogeneous components. As an example, the processing of one symbol by the SISO decoder incurs a complexity equivalent to 2104 Add(1,1), load(180) and store(130) operations per iteration. On the other hand, and considering a QPSK configuration (M=2), the complexity of the SISO demapper per modulated symbol per iteration is equivalent to 1470 Add(1,1), load(116) and store(16) operations. This table will thus enable us in the following sections to compute and to compare the overall complexity of the TBICM-SSD and TBICM-ID-SSD systems. It is worth noting from this table how the complexity of SISO demapping depends on the modulation order M while that of SISO decoding is independent from the system configuration.

This section discusses and analyzes the complexity of the two iterative modes at different modulation orders and code rates. The first subsection defines the complexity of each mode, while the second subsection analyzes the required number of iterations assuming identical complexity.

TBICM-SSD and TBICM-ID-SSD complexity definition

If the TBICM-SSD mode requires x iterations to process a frame composed of N _MSymb modulated symbols (equivalent to N_CSymb coded symbol), the complexity C₁for TBICM-SSD can be calculated as the sum of the complexity of one demapping process and x decoding processes.

where $C_{\mathrm{dem}}^{-}\left(M\right)$ designates the complexity of processing one modulated symbol, which depends on the constellation size, without taking into consideration the a priori computation, and C_decdesignates the complexity of processing one coded symbol.

Regarding the complexity of TBICM-ID-SSD, we consider the work of [11] which proposes an original iteration scheduling by reducing two demapping iterations with reasonable performance loss of less than 0.15 dB for all configurations. The authors have also shown that omitting only one demapping iteration will keep the error rate performance almost identical for number of iterations y>3. This latter scheme is adopted in this work and we denote the required number of iterations by yIDem _zEIDec, where z designates the extra decoding iterations.

Thus, the complexity C₂for TBICM-ID-SSD can be calculated as the sum of the complexity of y demapping processes and (y + z) decoding processes.

where $C_{\mathrm{dem}}^{+}\left(M\right)$ designates the complexity of processing one modulated symbol taking into consideration the a priori computation.

For the complexity evaluation of C_decand C_dem(M), the low complexity algorithms presented in Section System model and algorithms were thoroughly analyzed.

Considering the code rate R _c and the number of bits per modulated symbol M, the relation between the number of double binary coded symbols (N_CSymb) and the corresponding number of modulated symbols (N_MSymb) can be written as follows.

In addition to the modulation order and the code rate, a third parameter should be considered regarding the iterative demapping implementation choice. In this regard, two configurations should be analyzed. In the first configuration, denoted CASE 1, the Euclidean distances are re-calculated at each demapping iteration. While in the second configuration, denoted CASE 2, the computation of the Euclidean distances are done only once, at the first iteration, then stored and reused in later demapping iterations. Thus, CASE 1 implies higher arithmetic computations, however less memory access, than CASE 2.

Number of iterations for identical complexity

The final objective of this work is to illustrate for which system configuration it is more interesting to use TBICM-ID-SSD rather than TBICM-SSD. This means for which system configuration the complexity of TBICM-ID-SSD becomes lower than TBICM-SSD. Towards this objective, we analyze in this subsection the corresponding number of iterations if both modes have identical complexity. Identical complexity can be expressed as C₁=C₂. Using this equality and replacing C₁and C₂ by their expressions from equations (14) and (15) lead to the following equation:

This last equation allows to obtain the number of TBICM-ID-SSD iterations y=y_Limcorresponding to identical complexity for both modes. In fact, by replacing N_MSymb with equivalent number of N_CSymb(as expressed in Equation (16)) and by simplifying, Equation (17) becomes:

This equation can be used to compute individually y_Limfor identical arithmetic, identical read memory access or identical write memory access operations.

If we consider x=6, and for different modulation orders and code rates, Table 6 shows the required number of iterations y_Lim with no extra decoding iteration (z=0).

y_Limcan have positive values as well as negative values. Negative values mean that for the chosen configuration, TBICM-ID-SSD has always a higher complexity than TBICM-SSD. The positive values represent the limits for which performing less demapping iterations will lead to a lower complexity than TBCIM-SSD, and the inverse is true. Hence, it might be possible to perform less y iterations (y<y_Lim) with less complexity while having the same error correction capability than TBICM-SSD. In fact, Table 6 shows that this last situation can potentially happen for QPSK and QAM16 configurations where y_Limvaries in a higher range (between 2.9 and 5.8) than QAM64 and QAM256 configurations (most y_Limvalues are around 2 corresponding to identical arithmetic operations). This analysis will be extended in the next section taking into consideration error rate performance simulations.

The main motivation behind this analysis is to improve the receiver implementation quality by choosing the mode with the less complexity depending on each system configuration. In order to appreciate this study, an accurate evaluation of the complexity in terms of number and type of operations and memory access has been done in Section Number of iterations analysis for identical complexity.

TBICM-ID-SSD iterations, xIDec and yIDem respectively, iterative processing at the demapper side is shown to provide additional error correction [6]. Thus, for a considered number of x iterations, identical error rate performance results can be reached by using y iterations with y<x.

Complexity analysis for a chosen x

Figure 2 shows a BER comparison between the two iterative modes TBICM-SSD and TBICM-ID-SSD for two configurations: (1) QPSK, code rate $\frac{4}{5}$, erasure probability 0.15 and (2) QAM64, code rate $\frac{2}{3}$, non erasure. These parameters are chosen to represent clearly the two sets of curves in the same figure, the same behavior is seen for other configurations. The BER for x=6 iterations and for different configurations, can be seen as the result of y=3 and y=4 iterations for erasure and non erasure channel respectively. However, using results in [11], the complexity of 4IDem could be reduced to 3IDem _zEIDec with z=1.

BER performance comparison between TBICM-SSD and TBICM-ID-SSD for the transmission of 1536 information bits frame over Rayleigh fading channel with and without erasure. Different modulation schemes and code rates are considered, for 1 to 8 iterations.

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On the other hand, Table 6 shows that for QPSK modulation, the minimum number of required TBICM-ID-SSD iterations y_Limfor all code rates and for identical required arithmetic operations as 6IDec is y_Lim=4.2 with z=0. So using y=3<4.2 iterations will lead to less arithmetic complexity, meanwhile it has the same error correction capacity as illustrated in Figure 2 for (1).

Complexity improvements have been computed and summarized in Tables 7 and 8. These tables resume the achieved improvements comparing 6IDec to 3IDem _1EIDec and 3IDem _0EIDec respectively for all configurations. In the following we will explain first how these values are computed and then discuss the obtained results.

The complexity reduction ratio (G) is defined as the ratio of the difference in complexity between the two iterative modes to the complexity of TBICM-SSD. It corresponds to the gain ratio of using TBICM-ID-SSD rather than TBICM-SSD. G can be expressed as follows:

Using this equation and replacing C₁and C₂ by their expressions from Equations (14) and (15) lead to the following equation:

By replacing N_MSymb with equivalent number of N_CSymb(as expressed in Equation (16)) and by simplifying, Equation (20) becomes:

This last equation has been used to obtain individually the complexity reduction ratios of Tables 7 and 8 in terms of arithmetic, read memory access and write memory access operations. Positive values correspond to a decreasing in complexity, meanwhile negative values correspond to a an increasing in complexity.

In the following, we analyze the values of Table 7 which correspond to a no erasure channel. Similar behavior is seen in Table 8 for erasure channel.

For CASE 1, results show improvements in terms of number of arithmetic operations (up to 21.4%) and read access memory (up to 23.5%) for QPSK scheme. Higher modulation orders require the demapper to fetch symbols from higher constellation memory sizes, which lead to more complexity computations and memory accesses. An increasing in complexity is shown for QAM256 in terms of number of arithmetic operations (−207%) and read access memory (−108%). Moreover, Equation (21) shows that higher the code rate is, higher the benefits are. On the other hand, the improvements in write memory access (28.6% for R _c =1/2 and 30.6% for R _c =6/7) are positive for all modulations orders.

In fact, in the SISO demapper, write memory access is required only to store the extrinsic information which is composed of M×8 bits. This term is required per modulated symbol and when converted to the equivalent number per coded symbol (Equation (16)) for a fixed code rate, a constant value independent from M is obtained.

Similar behavior is shown for CASE 2, except for two points. The first one concerns the improvements in arithmetic operations and read memory access. In fact, compared to CASE 1, this configuration implies less arithmetic and more memory access operations in the SISO demapper which lead to more benefits for the former operations and less benefits for the latter (Equation (21)). The second point concerns the benefits in write memory access. In fact, besides the term M×8 bits, a value of 19×2^M is required to store the 2^MEuclidean distances quantized on 19 bits each. Therefore the benefits in write access memory operations will be less for high constellation sizes.

Taking an example of QAM64 and code rate $\frac{6}{7}$ for CASE 1 with no erasure. Table 8 shows an increasing in complexity in terms of arithmetic operations (−38.3%), meanwhile positive ratios are seen for read/write access memory. However, it should be noted that the number of required memory access are much less than the arithmetic operations. Thus, those latter are considered as the primary criteria for choosing between the two modes.

We can conclude from the results above that using TBICM-ID-SSD rather than TBICM-SSD for QPSK and QAM16 orders will lead to a significant complexity reduction for almost all code rates.

Finally, as the proposed adaptive iterative receiver targets to reduce the overall normalized processing complexity, this should lead a priori to improved power consumption, throughput and latency. However, analyzing the detailed gains in terms of throughput and latency depends on the heterogeneous architecture and the parallelism degree of the considered demapper and decoder algorithms.

Complexity analysis for different values of x

The second part of this study is to look to the gains for different values of x. To that end, and for presentation simplicity, we consider one system configuration which corresponds to QPSK, code rate $\frac{4}{5}$ and erasure probability 0.15.

Figure 3 illustrates the BER performance for both modes as a function of the number of iterations at E _b /N₀=9.5 dB. From this figure, we obtain Table 9 which illustrates the equivalent y iterations for different x values for identical error rate performances.

BER performance comparison between TBICM-SSD and TBICM-ID-SSD as a function of number of iterations for the transmission of 1536 information bits frame over Rayleigh fading channel with erasure probability equals to 0.15. QPSK modulation scheme with code rate $\frac{4}{5}$ and E _b /N₀=9.5 dB are considered.

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Using Table 9 and Equation (21), we obtain the complexity reduction curves of Figure 4. Only CASE 2 is considered for presentation simplicity, however the results are similar for CASE 1. The curves of Figure 4 show the variation of the benefits in number of arithmetic operations, read and write memory access as a function of the number of iterations x. In fact, Table 9 shows that for TBICM-SSD number of iterations x=1 the corresponding number of TBICM-ID-SSD iterations y=1. This corresponds to no feedback loop to the demapper, and thus, to identical complexity of the two modes TBICM-SSD and TBICM-ID-SSD. This result is illustrated by Figure 4 where the complexity reduction ratio G=0 for x=1. For x=2, the complexity reduction in terms of arithmetic operations and read access memory is about 10 and 2%, respectively. However, an increased need of write access memory is shown. This is due to the added complexity for storing the 2^MEuclidean distances computed at the first iteration. In fact, the difference in equivalent number of iterations x and y is not big enough to recover this memory write access overhead. However, for x>2, this difference becomes significant and the complexity reduction ratio increases almost linearly with x to reach between 50 to 60% for x=8. This can be explained from Table 9 where increasing x will increase y but with less speed to attain identical error rate performances.

The complexity reduction over iterations for using TBICM-ID-SSD rather than TBICM-SSD for QPSK with code rate $\frac{\mathbf{4}}{\mathbf{5}}$ , erasure probability 0.15, and CASE 2.

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In this article we have proposed a complexity adaptive iterative receiver performing TBICM-ID-SSD. For low and medium constellation sizes, feedback to the SISO demapper has shown to reduce the complexity in terms of computation and access memory at the receiver side for identical error rate performances. This constitutes a very interesting result as it demonstrates the opposite of what is commonly assumed. In fact, the number of normalized arithmetic operations is reduced in a range between 28.9 and 45.9% for QPSK configuration for using TBICM-ID-SSD rather than TBICM-SSD with 6 iterations over fading channel with erasures. Similarly, the number of read/write access memory is reduced in a range between 29.8% and 47%. This complexity reduction increases significantly for higher turbo decoding iterations and reduces consequently the power consumption of the iterative receiver. On the other had, for high modulation orders, as for QAM64 and QAM256, the TBICM-ID-SSD receiver should be configured in TBICM-SSD mode which provide less complexity for identical error rate performances.

Finally, it is worth to note that for very low error rates, TBICM-ID-SSD configuration should be used as it provides more error correction in the error floor region. Future work targets the extension of this analysis to other baseband iterative applications and its integration into available hardware prototypes.

Authors and Affiliations

1. Institut Mines-Telecom; Telecom Bretagne; UMR CNRS 3192 Lab-STICC Electronics Department, Technopôle Brest Iroise CS 83818, 29238, Brest, France

   Salim Haddad, Amer Baghdadi & Michel Jezequel

Corresponding author

Correspondence to Salim Haddad.

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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