Article

Multi-profile based code compression

Authors:

E. Wanderley Netto,

R. Azevedo,

P. Centoducatte,

G. AraujoAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 244 - 249

https://doi.org/10.1145/996566.996635

Published: 07 June 2004 Publication History

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Abstract

Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio, thus reducing power consumption and improving performance. This paper proposes an approach to mix static/dynamic instruction profiling in dictionary construction, so as to best exploit trade-offs in compression ratio/performance. Compressed instructions are stored as variable-size indices into fixed-size codewords, eliminating compressed code misalignments. Experimental results, using the Leon (SPARCv8) processor and a program mix from MiBench and Mediabench, show that our approach halves the number of cache accesses and power consumption while produces compression ratios as low as 56%.

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Cited By

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Lin CWang WChen JLin C(2019)Code Compression for Embedded SystemsEmbedded, Cyber-Physical, and IoT Systems10.1007/978-3-030-16949-7_6(115-147)Online publication date: 29-Jun-2019
https://doi.org/10.1007/978-3-030-16949-7_6
Chen PWu CJiang Y(2012)Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2011.12.00836:3(267-279)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1016/j.micpro.2011.12.008
Dias WMoreno Eda Silva Barreto R(2011)An approach for code compression in run time for embedded systemsProceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I10.5555/2075416.2075449(349-359)Online publication date: 24-Oct-2011
https://dl.acm.org/doi/10.5555/2075416.2075449
Show More Cited By

Index Terms

Multi-profile based code compression
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

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DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Lin CWang WChen JLin C(2019)Code Compression for Embedded SystemsEmbedded, Cyber-Physical, and IoT Systems10.1007/978-3-030-16949-7_6(115-147)Online publication date: 29-Jun-2019
https://doi.org/10.1007/978-3-030-16949-7_6
Chen PWu CJiang Y(2012)Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2011.12.00836:3(267-279)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1016/j.micpro.2011.12.008
Dias WMoreno Eda Silva Barreto R(2011)An approach for code compression in run time for embedded systemsProceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I10.5555/2075416.2075449(349-359)Online publication date: 24-Oct-2011
https://dl.acm.org/doi/10.5555/2075416.2075449
Lin CLin CWang W(2011)A power-aware code-compression design for RISC/VLIW architectureJournal of Zhejiang University SCIENCE C10.1631/jzus.C100032112:8(629-637)Online publication date: 2-Aug-2011
https://doi.org/10.1631/jzus.C1000321
Dias WMoreno Eda Silva Barreto R(2011)An Approach for Code Compression in Run Time for Embedded Systems – A Preliminary ResultsAlgorithms and Architectures for Parallel Processing10.1007/978-3-642-24650-0_30(349-359)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24650-0_30
Brorsson MCollin MHong SWolf WFlautner KKim T(2006)Adaptive and flexible dictionary code compression for embedded applicationsProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176776(113-124)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176760.1176776
Billo EAzevedo RAraujo GCentoducatte PNetto EGalup-Montoro CBampi SOrailoglu A(2005)Design of a decompressor engine on a SPARC processorProceedings of the 18th annual symposium on Integrated circuits and system design10.1145/1081081.1081113(110-114)Online publication date: 4-Sep-2005
https://dl.acm.org/doi/10.1145/1081081.1081113

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