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Article

Reducing reorder buffer complexity through selective operand caching

Authors:

Dmitry Ponomarev,

Kanad GhoseAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 235 - 240

https://doi.org/10.1145/871506.871564

Published: 25 August 2003 Publication History

Abstract

Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures, such as the Intel P6, the ROB also serves as a repository for the uncommitted results. In these designs, the ROB is a complex multi-ported structure that dissipates a significant percentage of the overall chip power. Recently, a mechanism was introduced for reducing the ROB complexity and its power dissipation through the complete elimination of read ports for reading out source operands. The resulting performance degradation is countered by caching the most recently produced results in a small set of associatively-addressed latches ("retention latches"). We propose an enhancement to the above technique by leveraging the notion of short-lived operands (values targeting the registers that are renamed by the time the instruction producing the value reaches the writeback stage). As much as 87% of all generated values are short lived for the SPEC 2000 benchmarks. Significant improvements in the utilization of retention latches, the overall performance, complexity and power are achieved by not caching short-lived values in the retention latches. As few as two retention latches allow all source operand read ports on the ROB to be completely eliminated with very little impact on performance.

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Cited By

Ponomarev DKucuk GErgin OGhose K(2004)Isolating Short-Lived Operands for Energy ReductionIEEE Transactions on Computers10.1109/TC.2004.1153:6(697-709)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.11
Ponomarev DKucuk GErgin OGhose K(2003)Reducing datapath energy through the isolation of short-lived operandsOceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)10.1109/PACT.2003.1238021(258-268)Online publication date: 2003
https://doi.org/10.1109/PACT.2003.1238021
Kucuk GErgin OPonomarev DGhose K(2003)Distributed reorder buffer schemes for low powerProceedings 21st International Conference on Computer Design10.1109/ICCD.2003.1240920(364-370)Online publication date: 2003
https://doi.org/10.1109/ICCD.2003.1240920

Index Terms

Reducing reorder buffer complexity through selective operand caching
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization

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Published In

cover image ACM Conferences

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Ponomarev DKucuk GErgin OGhose K(2004)Isolating Short-Lived Operands for Energy ReductionIEEE Transactions on Computers10.1109/TC.2004.1153:6(697-709)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.11
Ponomarev DKucuk GErgin OGhose K(2003)Reducing datapath energy through the isolation of short-lived operandsOceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)10.1109/PACT.2003.1238021(258-268)Online publication date: 2003
https://doi.org/10.1109/PACT.2003.1238021
Kucuk GErgin OPonomarev DGhose K(2003)Distributed reorder buffer schemes for low powerProceedings 21st International Conference on Computer Design10.1109/ICCD.2003.1240920(364-370)Online publication date: 2003
https://doi.org/10.1109/ICCD.2003.1240920

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