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An interactive logic synthesis system based upon AI techniques

Published: 01 January 1982 Publication History

Abstract

This paper proposes an interactive logic synthesis system which supports translation from behavioral to gate level. A design's specification described in the register transfer language DDL is translated into abstract objects. They are converted to macros representing logical structure and serving as technology independent goals which guide designers in synthesis phases. The system has knowledge about the technology adopted and can accommodate various know-how and design constraints to support the designer's tasks of PCB partition and logic synthesis. As a result, it greatly relieves designers from tedious tasks and makes it possible to explore alternative designs.

References

[1]
T. M. McWilliams and L. C. Widdoes, "SCALD: Structured Computer-Aided Logic Design", Proc. of 15th DA. Conf., pp.271-277, June 1978.
[2]
W. M. vanCleemput, "An Hierarchical Language for The Structured Description of Digital Systems", Proc. of 14th DA. Conf., pp.377-385, June 1977.
[3]
Keith A. Duke and Klim Maling, "ALEX: A Conversational Hierarchical Logic Design System", Proc. of 17th DA. Conf., pp.318-327, 1980.
[4]
J. C. Latomb, editor, "Artificial Intelligence and Pattern Recognition in Computer Aided Design", North-Holland, 1978.
[5]
Takao Saito, Takao Uehara, and Nobuaki Kawato, "A CAD System for Logic Design Based on Frames and Demons", Proc. of 18th DA. Conf., pp.451-456, July, 1981.
[6]
J. R. Duley and D. L. Dietmeyer, "A Digital System Design Language (DDL)," IEEE TC, Vol.C-17, 1968.
[7]
Nobuaki Kawato, Takao Saito, Fumihiro Maruyama, and Takao Uehara, "Design and Verification of Large-Scale Computers by Using DDL", Proc. of 16th DA. Conf., pp.360-366, June 1979.
[8]
Fumihiro Maruyama, Takao Uehara, Nobuaki Kawato, and Takao Saito, "Hardware Verification and Design Error Diagnosis", Proc. of FTC-10, pp.59-64, October 1980
[9]
Takao Uehara, Fumihiro Maruyama, Takao Saito, and Nobuaki Kawato, "DDL Verifier", Proc. of 5th International Conference on Computer hardware description languages, September 1981.
[10]
John A. Darringer, William. H. Joyner, Jr., C. Leonard Berman, Louise Trevillyan, "Logic Synthesis Through Local Transformations", IBM Journal of Research and Development, Vol. 25, No. 4, July, 1981.
[11]
Mark Jeffrey Stefik, "Planning with Constraints", Stanford University, Computer Science Department, Report No.STAN-CS-80-784, 1980.

Cited By

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  • (1986)A rule-based logic circuit synthesis system for CMOS gate arraysProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318109(594-600)Online publication date: 2-Jul-1986

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cover image ACM Conferences
DAC '82: Proceedings of the 19th Design Automation Conference
January 1982
919 pages

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IEEE Press

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Published: 01 January 1982

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  • (1986)A rule-based logic circuit synthesis system for CMOS gate arraysProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318109(594-600)Online publication date: 2-Jul-1986

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