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A hardware assisted design rule check architecture

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Larry SeilerAuthors Info & Claims

DAC '82: Proceedings of the 19th Design Automation Conference

Pages 232 - 238

Published: 01 January 1982 Publication History

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Abstract

This paper describes an architecture for design rule checking that uses a small amount of special purpose hardware to achieve a significant speed improvement over conventional methods. A fixed grid raster scan algorithm is used that allows checking of 45° angled edges at a modest cost in performance. Operations implemented directly in hardware include width checks, edge condition checks, boolean operations on masks, and shrinking and expansion of masks. Hardware support for rasterization is also provided. Software in a controlling processor handles all geometric data manipulation. This architecture should be able to check a simple set of design rules on a 300 mil square layout in one and one half minutes, if the controlling processor can provide data quickly enough. Layouts have been completed for two of four custom chips used in this architecture, and one has been fabricated and proven functional.

References

[1]

Baird, H.S., "Fast Algorithms for LSI Artwork Analysis," Proceedings of the 14th Design Automation Conference, pp. 303-311, June, 1977

Digital Library

Google Scholar

[2]

Rosenberg, M., Benbassat C., "CRITIC: An Integrated Circuit Design Rule Checking Program," Proceedings of the 11th Design Automation Workshop, Denver, pp. 14-18, June, 1974

Digital Library

Google Scholar

[3]

Mead, C., Conway, L., Introduction to VLSI Systems, Addison-Wesley, Massachusetts, 1980, pp.47-51

Digital Library

Google Scholar

[4]

Baker, C.M., Terman, T., "Tools for Verifying Integrated Circuit Designs," Lambda: the Magazine of VLSI Design, Volume 1, number 3, Fourth Quarter, 1980

Google Scholar

[5]

Baker, C.M., "Artwork Analysis Tools for Integrated Circuits," MIT/LCS/TR-239, Master's Thesis, Massachusetts Institute of Technology, 1980

Digital Library

Google Scholar

[6]

Giovanazzo, A., "A Mask Design Rule Checking System," Proceedings of the IEEE International Conference on Circuits and Computers, pp. 932-936, October, 1980

Google Scholar

[7]

Matheron, G., Random Sets and Integral Geometry, Wiley, New York, 1975, pp. 16-20

Google Scholar

[8]

Blank, T., Stefik, M., vanCleemput, W., "A Parallel Bit Map Processor Architecture for DA Algorithms," Proceedings of the 18th Design Automation Conference, Nashville, pp. 837-845, June, 1981

Digital Library

Google Scholar

[9]

Mudge, T., Lougheed, R., Teel, W., "Cellular Image Processing Techniques for Checking VLSI Circuit Layouts," Proceedings of the 1981 Conference on Information Sciences and Systems, The John Hopkins University, pp. 315-320, March, 1981

Google Scholar

[10]

Locanthi, B., "Object Oriented Raster Displays," Proceedings of the Caltech Conference on Very Large Scale Integration, pp. 215-225, January, 1979

Google Scholar

[11]

Bently, J.L., Haken, D., Hon, R.W., Statistics on VLSI Designs, CMU-CS-80-111, Department of Computer Science, Carnegie-Mellon University, April, 1980

Google Scholar

[12]

Tarolli, G., private communication, Digital Equipment Corporation, Hudson, Massachusetts

Google Scholar

Cited By

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Agrawal AGupta P(2009)Incremental analysis of large VLSI LayoutsIntegration, the VLSI Journal10.1016/j.vlsi.2008.06.00542:2(203-216)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1016/j.vlsi.2008.06.005
Luo ZMartonosi MAshar P(1999)An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule CheckingProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795846Online publication date: 21-Apr-1999
https://dl.acm.org/doi/10.5555/795658.795846
Won YSahni SEl-Zig Y(1990)A Hardware Accelerator for Maze RoutingIEEE Transactions on Computers10.1109/12.4629139:1(141-145)Online publication date: 1-Jan-1990
https://dl.acm.org/doi/10.1109/12.46291
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Index Terms

A hardware assisted design rule check architecture
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Very large scale integration design

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DAC '82: Proceedings of the 19th Design Automation Conference

January 1982

919 pages

ISBN:0897910206

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IEEE Press

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Published: 01 January 1982

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Agrawal AGupta P(2009)Incremental analysis of large VLSI LayoutsIntegration, the VLSI Journal10.1016/j.vlsi.2008.06.00542:2(203-216)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1016/j.vlsi.2008.06.005
Luo ZMartonosi MAshar P(1999)An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule CheckingProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795846Online publication date: 21-Apr-1999
https://dl.acm.org/doi/10.5555/795658.795846
Won YSahni SEl-Zig Y(1990)A Hardware Accelerator for Maze RoutingIEEE Transactions on Computers10.1109/12.4629139:1(141-145)Online publication date: 1-Jan-1990
https://dl.acm.org/doi/10.1109/12.46291
Bhat NNandy SThomas D(1989)Special purpose architecture for accelerating Bitmap DRCProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74501(674-677)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74501
Carlson ERutenbar RShaklee DNewton A(1988)Mask verification on the connection machineProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285752(134-140)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285752
Won YSahni SEl-ziq Y(1987)A hardware accelerator for maze routingProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.38014(800-806)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.38014
Hancock JDasGupta SThomas D(1986)Tutorial on parallel processing for design automation applications (tutorial session)Proceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318025(69-77)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318025
Kane RSahni SLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)A systolic design rule checkerProceedings of the 21st Design Automation Conference10.5555/800033.800803(243-250)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800803
Szymanski TVan Wyk CRadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)Space efficient algorithms for VLSI artwork analysisProceedings of the 20th Design Automation Conference10.5555/800032.800754(734-739)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800754
Gupta ARadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)ACEProceedings of the 20th Design Automation Conference10.5555/800032.800751(721-725)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800751
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Abstract

References

Cited By

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Recommendations

A configurable hardware/software system for design rule checking

An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking

Magic's incremental design-rule checker

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