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DORA:: CAD interface to automatic diagnostics

Published: 01 January 1982 Publication History

Abstract

This paper will discuss a family of CAD tools supporting automatic diagnosis and the usage of those tools in Western Electric Company (WECo) testing. The CAD tools described in this paper are part of a package developed at the Engineering Research Center (ERC), Princeton, New Jersey. The Diagnostic Organization and Retrieval Algorithms (DORA) System is a complex of programs which provide audited test programs and diagnostic data files from the results of LAMP (Logic Analyzer for Maintenance Planning)1 circuit simulation. DORA supports manufacturing and repair test facilities in all Divisions of Western Electric that produce circuit packs or digital custom devices. Improved engineering productivity in Bell Laboratories and Western Electric, efficient use of capital intensive test hardware, and reduced diagnostic costs are the goals of this package.

References

[1]
S. G. Chappel, C. H. Elmendorf, L. D. Schmidt, "LAMP: Logic Circuit Simulators," BSTJ, liii, 8, October, 1974, pp. 1451-1476.
[2]
K. To, R. E. Tulloss, "The Dictionary Organization and Retrieval Algorithm," Proceedings 1974 Semiconductor Test Symposium: Memory & LSI, Cherry Hill, November 5-7, 1974, pp. 189-215.
[3]
R. E. Tulloss, "Size Optimization of Fault Dictionaries," Proceedings 1978 Semiconductor Test Conference, Cherry Hill, October, 1978, pp. 264-265.
[4]
R. E. Tulloss, "Fault Dictionary Compression: Recognizing When a Fault May be Unambiguously Represented by a Single Failure Detection," Proceedings 1980 Test Conference, Philadelphia, November, 1980, pp. 368-370.
[5]
R. W. Allen, C. D. Chen, M. M. Ervin-Willis, K. R. Rahlfs, R. E. Tulloss, S. L. Wu, "DORA," Proceedings 1981 Test Conference, Philadelphia, October, 1981, pp. 555-560.
[6]
G. Persky, D. Deutsch, D. G. Schweikert, "LTX-A System for the Directed Automatic Design of LSI Circuits," Proceedings 13th Design Automation Conference, San Francisco, 1976, pp. 399-407.
[7]
C. V. Hoben, J. E. Neuhausel, K. To, "A Technique for Locating Faults in Digital Circuit Packs," The Western Electric Engineer, xx, 3, July, 1976, pp. 15-23.
[8]
D. B. Armstrong, "Testing PBX Circuit Packs," Bell Laboratories Record, liii, 7, July-August, 1975, pp. 307-311.
[9]
H. Y. Chung, E. G. Manning, G. Metze, Fault Diagnosis in Digital Systems, Wiley-Interscience, 1970.
[10]
A. D. Friedman, P. R. Menon, Fault Detection in Digital Circuits, Prentice Hall, 1971.
[11]
M. A. Breuer, A. D. Friedman, Diagnosis & Reliable Design of Digital Systems, Computer Science Press, Inc., 1976.
[12]
R. L. Wadsack, "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," BSTJ, 57, No. 5 (May-June, 1978), pp. 1449-1474.
[13]
T. W. Williams, K. P. Parker, "Design for Testability - A Survey," IEEE Transactions on Computers, C-31, 1, January, 1982, pp. 2-15.

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cover image ACM Conferences
DAC '82: Proceedings of the 19th Design Automation Conference
January 1982
919 pages

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IEEE Press

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Published: 01 January 1982

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