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Access conflicts in multiprocessor memories queueing models and simulation studies

Authors:

Ingrid Y. Bucher,

Donald A. CalahanAuthors Info & Claims

ICS '90: Proceedings of the 4th international conference on Supercomputing

Pages 428 - 438

https://doi.org/10.1145/77726.255184

Published: 01 June 1990 Publication History

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Abstract

The performance of an interleaved common memory accessed uniformly by multiple processors is modeled by queueing methods. The model includes access conflicts at the bank level while assuming an ideal access network.

A scaling relation is derived that is generally valid and indicates that memory access delays are given by the product of the bank reservation time and a function of the memory utilization, which is given by the average number of access requests arriving at a bank per bank reservation time. For light memory traffic, access delays are proportional to the square of the bank reservation time and the ratio of the number of active memory access streams to the number of memory banks.

Assuming random access patterns, an open and a closed queueing model are developed that are validated by simulations. Delay dependence on bank reservation time is quadratic for light loads and linear for very heavy loads.

A heuristic extension of our model for vector accessing of banks in sequential mode is proposed.

References

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Bucher, I. Y. and M. L. Simmons, "Measurements of Memory Access Contentions in Multiple Vector Proeessor Systems," to be published.

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Cited By

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Peiron MValero MAyguadé ELang T(1995)Vector multiprocessors with arbitrated memory accessACM SIGARCH Computer Architecture News10.1145/225830.22443523:2(243-252)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1145/225830.224435
Peiron MValero MAyguadé ELang TPatterson D(1995)Vector multiprocessors with arbitrated memory accessProceedings of the 22nd annual international symposium on Computer architecture10.1145/223982.224435(243-252)Online publication date: 1-Jul-1995
https://dl.acm.org/doi/10.1145/223982.224435
Yang QYang T(1995)A Memory Interference Model for Regularly Patterned Multiple Stream Vector AccessesIEEE Transactions on Parallel and Distributed Systems10.1109/71.3823206:5(520-530)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1109/71.382320
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Access conflicts in multiprocessor memories queueing models and simulation studies

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Information

Published In

ICS '90: Proceedings of the 4th international conference on Supercomputing

June 1990

492 pages

ISBN:0897913698

DOI:10.1145/77726

Chairmen:
Ahmed Sameh
Univ. of Illinois
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

ACM SIGARCH Computer Architecture News Volume 18, Issue 3b
Special Issue: Proceedings of the 4th international conference on Supercomputing
Sept. 1990
489 pages
ISSN:0163-5964
DOI:10.1145/255129
Chairmen:
Ahmed Sameh
Univ. of Illinois at Urbana-Champaign, Urbana
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands
Issue’s Table of Contents

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Association for Computing Machinery

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Publication History

Published: 01 June 1990

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IC'90: ACM SIGARCH International Conference on Supercomputing

June 11 - 15, 1990

Amsterdam, The Netherlands

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

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Peiron MValero MAyguadé ELang T(1995)Vector multiprocessors with arbitrated memory accessACM SIGARCH Computer Architecture News10.1145/225830.22443523:2(243-252)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1145/225830.224435
Peiron MValero MAyguadé ELang TPatterson D(1995)Vector multiprocessors with arbitrated memory accessProceedings of the 22nd annual international symposium on Computer architecture10.1145/223982.224435(243-252)Online publication date: 1-Jul-1995
https://dl.acm.org/doi/10.1145/223982.224435
Yang QYang T(1995)A Memory Interference Model for Regularly Patterned Multiple Stream Vector AccessesIEEE Transactions on Parallel and Distributed Systems10.1109/71.3823206:5(520-530)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1109/71.382320
van Gemund AGurd JJalby W(1994)Compiling performance models from parallel programsProceedings of the 8th international conference on Supercomputing10.1145/181181.181546(303-312)Online publication date: 16-Jul-1994
https://dl.acm.org/doi/10.1145/181181.181546
Peiron MValero MAyguadé EGurd JJalby W(1994)Synchronized access to streams in SIMD vector multiprocessorsProceedings of the 8th international conference on Supercomputing10.1145/181181.181204(23-32)Online publication date: 16-Jul-1994
https://dl.acm.org/doi/10.1145/181181.181204
Smith JTaylor WKennedy KPolychronopoulos C(1992)Characterizing memory performance in vector multiprocessorsProceedings of the 6th international conference on Supercomputing10.1145/143369.143379(35-44)Online publication date: 1-Aug-1992
https://dl.acm.org/doi/10.1145/143369.143379
Ganesan RWeiss S(1992)Scalar Memory References in Pipelined MultiprocessorsIEEE Transactions on Software Engineering10.1109/32.12031818:1(78-86)Online publication date: 1-Jan-1992
https://dl.acm.org/doi/10.1109/32.120318
Bucher ISimmons MElliott R(1991)Measurement of memory access contentions in multiple vector processor systemsProceedings of the 1991 ACM/IEEE conference on Supercomputing10.1145/125826.126197(806-817)Online publication date: 1-Aug-1991
https://dl.acm.org/doi/10.1145/125826.126197
Xu DChu CLiu CWang YZhou XZhang LLiang HLi HMohsenin TZhao WChen YMutlu O(2020)Multi-task Scheduling for PIM-based Heterogeneous Computing SystemProceedings of the 2020 on Great Lakes Symposium on VLSI10.1145/3386263.3406946(457-462)Online publication date: 7-Sep-2020
https://dl.acm.org/doi/10.1145/3386263.3406946
Pang DXu DWang YLiang H(2018)MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System2018 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia.2018.00015(25-30)Online publication date: Aug-2018
https://doi.org/10.1109/ITC-Asia.2018.00015
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