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ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory

Online AM: 04 November 2024 Publication History

Abstract

The CXL (Compute Express Link) technology is an emerging memory interface with high-level commands. Recent studies applied the CXL memory expanding technique to mitigate the capacity limitation of the conventional DDRx memory. Unlike the prior studies to use the CXL memory as the capacity expander, this study proposes to use the CXL-based memory as a secure main memory device, while removing the conventional memory. In the conventional DDRx memory, to provide confidentiality, integrity, replay protection, and obliviousness, costly mechanisms such as counter-based integrity trees and location shuffling by ORAM (Oblivious RAM) are used. Such mechanisms incur significant performance degradation in the current DDR-based memory systems, and their costs increase as the capacity of the memory increases. To mitigate the performance degradation, the prior work proposed an obfuscated channel for a secure memory module enclosing its controller in the package. Based on the approach, we propose a secure CXL-only memory architecture called ShieldCXL. It uses the channel encryption and integrity protection mechanism of the CXL interface to provide a practical ORAM while supporting confidentiality, integrity, and replay protection from physical attacks and rowhammers. To protect the PCIe-connected memory expanding board, this study proposes to use the standard physical sealing technique to detect physical intrusion. To mitigate the increased latency with the sealed CXL memory module, the study further optimizes performance by adopting an in-package DRAM cache. In addition, this study investigates destination obfuscation when a CXL switch is used to route among multiple hosts and memory devices. The evaluation shows that ShieldCXL provides 9.16x performance improvements over the prior ORAM technique.

References

[1]
Shaizeen Aga and Satish Narayanasamy. 2017. InvisiMem: Smart Memory Defenses for Memory Bus Side Channel. In Proceedings of the International Symposium on Computer Architecture (ISCA’17). 94–106.
[2]
Amro Awad, Yipeng Wang, Deborah Shands, and Yan Solihin. 2017. Obfusmem: A low-overhead access obfuscation for trusted memories. In Proceedings of the International Symposium on Computer Architecture (ISCA’17). 107–119.
[3]
Shivam Bhasin, Paolo Maistri, and Francesco Regazzoni. 2014. Malicious wave: A survey on actively tampering using electromagnetic glitch. In Proceedings of the International Symposium on Electromagnetic Compatibility. 318–321.
[4]
J. A. Busby, E. N. Cohen, E. A. Dames, J. Doherty, S. Dragone, D. Evans, M. J. Fisher, N. Hadzic, C. Hagleitner, A. J. Higby, M. D. Hocker, L. S. Jagich, M. J. Jordan, R. Kisley, K. D. Lamb, M. D. Marik, J. Mayfield, T. E. Morris, T. D. Needham, W. Santiago-Fernandez, V. Urban, T. Visegrady, and K. Werner. 2020. The IBM 4769 Cryptographic Coprocessor. IBM Journal of Research and Development 64, 5/6 (2020).
[5]
Businesswire. 2021. PLDA and AnalogX Announce Market-leading CXL 2.0 Solution featuring Ultra-low Latency and Power. https://www.businesswire.com/news/home/20210602005484/en/PLDA-and-AnalogX-Announce-Market-leading-CXL-2.0-Solution-featuring-Ultra-low-Latency-and-Power.
[6]
Irina Calciu, M Talha Imran, Ivan Puddu, Sanidhya Kashyap, Hasan Al Maruf, Onur Mutlu, and Aasheesh Kolli. 2021. Rethinking software runtimes for disaggregated memory. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’21). 79–92.
[7]
Albert Cho, Anish Saxena, Moinuddin Qureshi, and Alexandros Daglis. 2024. COAXIAL: A CXL-Centric Memory System for Scalable Servers. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC’24).
[8]
CXL Consortium. 2024. CXL 3.1 Specification. https://computeexpresslink.org/cxl-specification/.
[9]
CXL Consortium. 2024. Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL. https://computeexpresslink.org/blog/integrity-and-data-encryption-ide-trends-and-verification-challenges-in-cxl-compute-express-link-2797/.
[10]
Victor Costan and Srinivas Devadas. 2016. Intel SGX explained. In Cryptology ePrint Archive.
[11]
Pham-Khoi Dong, Hung K. Nguyen, and Xuan-Tu Tran. 2019. A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications. In Proceedings of the International Symposium on Communications and Information Technologies (ISCIT’19). 196–200.
[12]
A. Fakhrzadehgan, P. Ramrakhyani, M. K. Qureshi, and M. Erez. 2023. SecDDR: Enabling Low-Cost Secure Memories by Protecting the DDR Interface. In Proceedings of the International Conference on Dependable Systems and Networks (DSN’23). 14–27.
[13]
Elischa Ferres, Vincent Immler, Alexander Utz, Alexander Stanitzki, Reneé Lerch, and Rainer Kokozinski. 2018. Capacitive Multi-Channel Security Sensor IC for Tamper-Resistant Enclosures. In 2018 IEEE SENSORS. 1–4.
[14]
Christopher W Fletcher, Ling Ren, Albert Kwon, Marten Van Dijk, and Srinivas Devadas. 2015. Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’15). 103–116.
[15]
Christopher W. Fletchery, Ling Ren, Xiangyao Yu, Marten Van Dijk, Omer Khan, and Srinivas Devadas. 2014. Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA’14). 213–224.
[16]
Distributed Management Task Force. 2023. Secured Messages using SPDM Specification. https://www.dmtf.org/sites/default/files/standards/documents/DSP0277_1.1.0.pdf/.
[17]
Wilfred Gomes, Slade Morgan, Boyd Phelps, Tim Wilson, and Erik Hallnor. 2022. Meteor Lake and Arrow Lake Intel Next-Gen 3D Client Architecture Platform with Foveros. In Hot Chips Symposium (HCS’22). 1–40.
[18]
Donghyun Gouk, Sangwon Lee, Miryeong Kwon, and Myoungsoo Jung. 2022. Direct access, High-Performance memory disaggregation with DirectCXL. In Proceedings of the USENIX Annual Technical Conference (ATC’22). 287–294.
[19]
Juncheng Gu, Youngmoon Lee, Yiwen Zhang, Mosharaf Chowdhury, and Kang G Shin. 2017. Efficient memory disaggregation with infiniswap. In Proceedings of the USENIX Symposium on Networked Systems Design and Implementation (NSDI’17). 649–667.
[20]
Andrew Huang. 2002. Keeping secrets in hardware: The microsoft xboxtm case study. In International Workshop on Cryptographic Hardware and Embedded Systems. 213–227.
[21]
Jinghan Huang, Jiaqi Lou, Srikar Vanavasam, Xinhao Kong, Houxiang Ji, Ipoom Jeong, Danyang Zhuo, Eun Kyung Lee, and Nam Sung Kim. 2024. HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing. In Proceedings of the International Symposium on Computer Architecture (ISCA’24). 613–627.
[22]
Michael Hutter and Jörn-Marc Schmidt. 2014. The temperature side channel and heating fault attacks. In Smart Card Research and Advanced Applications. 219–235.
[23]
Hypersecu. 2020. HYP2003 Cryptographic Module. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp3602.pdf.
[24]
IBM. 2023. IBM 4770 PCIe Cryptographic Coprocessor Hardware Security Module. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp4558.pdf.
[25]
Infineon. 2022. Infineon Trusted Platform Module 2.0 SLB 9670 cryptographic module. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp3492.pdf.
[26]
Intel. 2023. How Does the DRAM Caching Work in Memory Mode Using Intel® Optane™ Persistent Memory?https://www.intel.com/content/www/us/en/support/articles/000055901/memory-and-storage/intel-optane-persistent-memory.html.
[27]
Intel. 2023. Intel Xeon CPU Max Series Configuration and Tuning Guide. https://cdrdv2-public.intel.com/769060/354227-intel-xeon-cpu-max-series-configuration-and-tuning-guide.pdf.
[28]
Intel. 2023. Intel® Xeon® CPU Max Series. https://www.intel.com/content/www/us/en/products/docs/processors/xeon/xeon-max-series-product-brief.html.
[29]
Intel. 2024. Intel® Trust Domain Extensions (Intel TDX). https://www.intel.com/content/www/us/en/developer/tools/trust-domain-extensions/overview.html.
[30]
Phil Isaacs, Thomas Morris Jr, Michael J Fisher, and Keith Cuthbert. 2013. Tamper Proof, Tamper Evident Encryption Technology. In Pan Pacific Symposium.
[31]
Mohammad Saiful Islam, Mehmet Kuzu, and Murat Kantarcioglu. 2012. Access pattern disclosure on searchable encryption: ramification, attack and mitigation. In Ndss, Vol.  20. 12.
[32]
Junhyeok Jang, Hanjin Choi, Hanyeoreum Bae, Seungjun Lee, Miryeong Kwon, and Myoungsoo Jung. 2023. CXL-ANNS: Software-Hardware Collaborative Memory Disaggregation and Computation for Billion-Scale Approximate Nearest Neighbor Search. In Proceedings of the USENIX Annual Technical Conference (ATC’23). 585–600.
[33]
David Kaplan, Jeremy Powell, and Tom Woller. 2016. AMD memory encryption. White paper (2016), 13.
[34]
The kernel development community. 2024. Linux Kernel Driver APIs - Compute Express Link Memory Devices. https://docs.kernel.org/driver-api/cxl/memory-devices.html.
[35]
Sanjeev Khushu and Wilfred Gomes. 2019. Lakefield: Hybrid cores in 3D Package. In Hot Chips Symposium (HCS’19). 1–20.
[36]
Jonghyeon Kim, Wonkyo Choe, and Jeongseob Ahn. 2021. Exploring the Design Space of Page Management for Multi-Tiered Memory Systems. In Proceedings of the USENIX Annual Technical Conference (ATC’21). 715–728.
[37]
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ACM SIGARCH Computer Architecture News 42, 3 (2014).
[38]
Vladimir Kiriansky, Ilia Lebedev, Saman Amarasinghe, Srinivas Devadas, and Joel Emer. 2018. DAWG: A defense against cache timing attacks in speculative execution processors. In Proceedings of the International Symposium on Microarchitecture (MICRO’18). 974–987.
[39]
Paul Kocher, Joshua Jaffe, Benjamin Jun, and Pankaj Rohatgi. 2011. Introduction to differential power analysis. Journal of Cryptographic Engineering 1 (2011).
[40]
Miryeong Kwon, Junhyeok Jang, Hanjin Choi, Sangwon Lee, and Myoungsoo Jung. 2023. Failure Tolerant Training With Persistent Memory Disaggregation Over CXL. IEEE Micro 43, 2 (2023).
[41]
Andrew Kwong, Daniel Genkin, Daniel Gruss, and Yuval Yarom. 2020. Rambleed: Reading bits in memory without accessing them. In Proceedings of the Symposium on Security and Privacy (SP’20). 695–711.
[42]
Sunho Lee, Jungwoo Kim, Seonjin Na, Jongse Park, and Jaehyuk Huh. 2022. TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’22). 229–243.
[43]
Taehyung Lee, Sumit Kumar Monga, Changwoo Min, and Young Ik Eom. 2023. Memtis: Efficient Memory Tiering with Dynamic Page Classification and Page Size Determination. In Proceedings of the Symposium on Operating Systems Principles (SOSP’23). 17–34.
[44]
Baptiste Lepers and Willy Zwaenepoel. 2023. Johnny Cache: the End of DRAM Cache Conflicts (in Tiered Main Memory Systems). In Proceedings of the USENIX Symposium on Operating Systems Design and Implementation (OSDI’23). 519–534.
[45]
Huaicheng Li, Daniel S. Berger, Lisa Hsu, Daniel Ernst, Pantea Zardoshti, Stanko Novakovic, Monish Shah, Samir Rajadnya, Scott Lee, Ishwar Agarwal, Mark D. Hill, Marcus Fontoura, and Ricardo Bianchini. 2023. Pond: CXL-based memory pooling systems for cloud platforms. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’23). 574–587.
[46]
Shang Li, Zhiyuan Yang, Dhiraj Reddy, Ankur Srivastava, and Bruce Jacob. 2020. DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator. IEEE Computer Architecture Letters 19, 2.
[47]
Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown. arXiv preprint arXiv:1801.01207(2018).
[48]
Fangfei Liu, Qian Ge, Yuval Yarom, Frank Mckeen, Carlos Rozas, Gernot Heiser, and Ruby B Lee. 2016. Catalyst: Defeating last-level cache side channel attacks in cloud computing. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA’16). 406–418.
[49]
Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, and Ruby B Lee. 2015. Last-level cache side-channel attacks are practical. In Proceedings of the symposium on security and privacy (SP’15). 605–622.
[50]
Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanovic, John Kubiatowicz, and Dawn Song. 2013. Phantom: Practical oblivious computation in a secure processor. In Proceedings of the ACM SIGSAC conference on Computer & communications security (CCS’13). 311–324.
[51]
Hasan Al Maruf, Hao Wang, Abhishek Dhanotia, Johannes Weiner, Niket Agarwal, Pallab Bhattacharya, Chris Petersen, Mosharaf Chowdhury, Shobhit Kanaujia, and Prakash Chauhan. 2023. TPP: Transparent page placement for CXL-enabled tiered-memory. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’23). 742–755.
[52]
Thomas S Messerges. 2000. Securing the AES finalists against power analysis attacks. In International Workshop on Fast Software Encryption. 150–164.
[53]
Thomas S Messerges, Ezzy A Dabbish, and Robert H Sloan. 1999. Investigations of Power Analysis Attacks on Smartcards.Smartcard 99(1999).
[54]
Motorola. 2019. ASTRO CDEM Motorola Advanced Crypto Engine. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp3512.pdf.
[55]
Seonjin Na, Jungwoo Kim, Sunho Lee, and Jaehyuk Huh. 2024. Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’24). 204–217.
[56]
Seonjin Na, Sunho Lee, Yeonjae Kim, Jongse Park, and Jaehyuk Huh. 2021. Common Counters: Compressed Encryption Counters for Secure GPU Memory. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’21). 1–13.
[57]
National Institute of Standards and Technology (NIST). 2019. FIPS 140-3, Security Requirements for Cryptographic Modules. https://csrc.nist.gov/pubs/fips/140-3/final.
[58]
National Institute of Standards and Technology (NIST). 2024. Implementation Guidance for FIPS 140-3 and the Cryptographic Module Validation Program. https://csrc.nist.gov/csrc/media/Projects/cryptographic-module-validation-program/documents/fips%20140-3/FIPS%20140-3%20IG.pdf.
[59]
National Institute of Standards, Technology (NIST), and Morris J. Dworkin. 2015. SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions. (2015).
[60]
Sang-Soo Park, KyungSoo Kim, Jinin So, Jin Jung, Jonggeon Lee, Kyoungwan Woo, Nayeon Kim, Younghyun Lee, Hyungyo Kim, Yongsuk Kwon, Jinhyun Kim, Jieun Lee, YeonGon Cho, Yongmin Tai, Jeonghyeon Cho, Hoyoung Song, Jung Ho Ahn, and Nam Sung Kim. 2024. An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’24).
[61]
Intellect Partners. 2023. Migration from Hybrid Memory Cube (HMC) to High-Bandwidth Memory (HBM). https://intellect-partners.com/blog/migration-from-hybrid-memory-cube-hmc-to-high-bandwidth-memory-hbm.
[62]
Rachit Rajat, Yongqin Wang, and Murali Annavaram. 2022. PageORAM: An Efficient DRAM Page Aware ORAM Strategy. In Proceedings of the International Symposium on Microarchitecture (MICRO’22). 91–107.
[63]
Rachit Rajat, Yongqin Wang, and Murali Annavaram. 2023. Laoram: A look ahead oram architecture for training large embedding tables. In Proceedings of the International Symposium on Computer Architecture (ISCA’23). 1–15.
[64]
Rambus. 2024. DDR5 Server DIMM Chipset. https://www.rambus.com/memory-interface-chips/ddr5-dimm-chipset/.
[65]
Realia. 2018. Cryptosec Dekaton. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp3329.pdf.
[66]
Ling Ren, Xiangyao Yu, Christopher W Fletcher, Marten Van Dijk, and Srinivas Devadas. 2013. Design space exploration and optimization of path oblivious ram in secure processors. In Proceedings of the International Symposium on Computer Architecture (ISCA’13). 571–582.
[67]
Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, and Yan Solihin. 2007. Using address independent seed encryption and bonsai merkle trees to make secure processors os-and performance-friendly. In Proceedings of the International Symposium on Microarchitecture (MICRO’07). 183–196.
[68]
Zhenyuan Ruan, Malte Schwarzkopf, Marcos K Aguilera, and Adam Belay. 2020. AIFM: High-Performance, Application-Integrated far memory. In Proceedings of the USENIX Symposium on Operating Systems Design and Implementation (OSDI’20). 315–332.
[69]
Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Jose A. Joao, and Moinuddin K. Qureshi. 2018. Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories. In Proceedings of the International Symposium on Microarchitecture (MICRO’18). 416–427.
[70]
Daniel Sanchez and Christos Kozyrakis. 2013. ZSim: Fast and accurate microarchitectural simulation of thousand-core systems. ACM SIGARCH Computer architecture news 41, 3 (2013).
[71]
NXP Semiconductors. 2020. NXP Semiconductors JCOP4 P71 cryptographic module. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp3746.pdf.
[72]
Wisekey Semiconductors. 2018. VaultIC420 and VaultIC460. https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp3533.pdf.
[73]
Sean W. Smith and Steve Weingart. 1999. Building a High-performance, Programmable Secure Coprocessor. Comput. Netw. 31, 9 (1999).
[74]
Chihun Song, Michael Jaemin Kim, Tianchen Wang, Houxiang Ji, Jinghan Huang, Ipoom Jeong, Jaehyun Park, Hwayong Nam, Minbok Wi, Jung Ho Ahn, and Nam Sung Kim. 2024. TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’24). 981–998.
[75]
Emil Stefanov, Marten van Dijk, Elaine Shi, T-H Hubert Chan, Christopher Fletcher, Ling Ren, Xiangyao Yu, and Srinivas Devadas. 2018. Path ORAM: an extremely simple oblivious RAM protocol. Journal of the ACM (JACM) 65, 4 (2018).
[76]
Lisa Su and Sam Naffziger. 2023. 1.1 Innovation For the Next Decade of Compute Efficiency. In Proceedings of the International Solid-State Circuits Conference (ISSCC’23). 8–12.
[77]
Yan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper, Chihun Song, Jinghan Huang, Houxiang Ji, Siddharth Agarwal, Jiaqi Lou, Ipoom Jeong, Ren Wang, Jung Ho Ahn, Tianyin Xu, and Nam Sung Kim. 2023. Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. In Proceedings of the International Symposium on Microarchitecture (MICRO’23). 105–121.
[78]
Meysam Taassori, Ali Shafiee, and Rajeev Balasubramonian. 2018. VAULT: Reducing paging overheads in SGX with efficient integrity verification structures. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’18). 665–678.
[79]
Mingtian Tan, Junpeng Wan, Zhe Zhou, and Zhou Li. 2021. Invisible Probe: Timing Attacks with PCIe Congestion Side-channel. In Proceedings of the symposium on Security and Privacy (SP’21). 322–338.
[80]
Xconn Technologies. 2024. XConn: CXL Switches for AI. https://www.youtube.com/watch?v=oCldo3GgJKg.
[81]
Daniel Townley, Kerem Arıkan, Yu David Liu, Dmitry Ponomarev, and Oğuz Ergin. 2022. Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks. In Proceedings of the USENIX Security Symposium (Security’22). 2839–2856.
[82]
Yuval Yarom and Katrina Falkner. 2014. FLUSH+ RELOAD: A high resolution, low noise, l3 cache Side-Channel attack. In Proceedings of the USENIX security symposium (Security’14). 719–732.
[83]
Wonsup Yoon, Jisu Ok, Jinyoung Oh, Sue Moon, and Youngjin Kwon. 2023. DiLOS: Do Not Trade Compatibility for Performance in Memory Disaggregation. In Proceedings of the European Conference on Computer Systems (Eurosys’23). 266–282.
[84]
Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher Fletcher, Albert Kwon, Marten Van Dijk, and Srinivas Devadas. 2015. Proram: dynamic prefetcher for oblivious ram. In Proceedings of the International Symposium on Computer Architecture (ISCA’15). 616–628.
[85]
Shougang Yuan, Amro Awad, Ardhi Wiratama Baskara Yudha, Yan Solihin, and Huiyang Zhou. 2022. Adaptive Security Support for Heterogeneous Memory on GPUs. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’22). 213–228.
[86]
Xiaotong Zhuang, Tao Zhang, and Santosh Pande. 2004. HIDE: an infrastructure for efficiently protecting information leakage on the address bus. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’04). 72–84.

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    cover image ACM Transactions on Architecture and Code Optimization
    ACM Transactions on Architecture and Code Optimization Just Accepted
    EISSN:1544-3973
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    Publication History

    Online AM: 04 November 2024
    Accepted: 26 October 2024
    Revised: 11 October 2024
    Received: 21 June 2024

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    Author Tags

    1. Hardware security
    2. Access obfuscation
    3. CXL

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