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Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders

Authors:

Ebrahim Farahmand,

Muhammad Abdullah Hanif,

Muhammad ShafiqueAuthors Info & Claims

ACM Transactions on Embedded Computing Systems, Volume 22, Issue 6

Article No.: 106, Pages 1 - 32

https://doi.org/10.1145/3625686

Published: 09 November 2023 Publication History

Abstract

Approximate computing is an emerging paradigm to improve the power and performance efficiency of error-resilient applications. As adders are one of the key components in almost all processing systems, a significant amount of research has been carried out toward designing approximate adders that can offer better efficiency than conventional designs; however, at the cost of some accuracy loss. In this article, we highlight a new class of energy-efficient approximate adders, namely, Heterogeneous Block-based Approximate Adders (HBAAs), and propose a generic configurable adder model that can be configured to represent a particular HBAA configuration. An HBAA, in general, is composed of heterogeneous sub-adder blocks of equal length, where each sub-adder can be an approximate sub-adder and have a different configuration. The sub-adders are mainly approximated through inexact logic and carry truncation. Compared to the existing design space, HBAAs provide additional design points that fall on the Pareto-front and offer a better quality-efficiency tradeoff in certain scenarios. Furthermore, to enable efficient design space exploration based on user-defined constraints, we propose an analytical model to efficiently evaluate the Probability Mass Function (PMF) of approximation error and other error metrics, such as Mean Error Distance (MED), Normalized Mean Error Distance (NMED), and Error Rate (ER) of HBAAs. The results show that HBAA configurations can provide around 15% reduction in area and up to 17% reduction in energy compared to state-of-the-art approximate adders.

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Cited By

Hanif MArous AShafique M(2024)DREAMx: A Data-Driven Error Estimation Methodology for Adders Composed of Cascaded Approximate UnitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344720943:11(3348-3357)Online publication date: Nov-2024
https://doi.org/10.1109/TCAD.2024.3447209

Index Terms

Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits

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Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 22, Issue 6

November 2023

428 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3632298

Editor:
Tulika Mitra
National University of Singapore, Singapore

Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 09 November 2023

Online AM: 28 September 2023

Accepted: 06 September 2023

Revised: 03 September 2023

Received: 24 August 2022

Published in TECS Volume 22, Issue 6

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Cited By

Hanif MArous AShafique M(2024)DREAMx: A Data-Driven Error Estimation Methodology for Adders Composed of Cascaded Approximate UnitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344720943:11(3348-3357)Online publication date: Nov-2024
https://doi.org/10.1109/TCAD.2024.3447209

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