PCIE-Based Shared Memory Technology between BMC and CPU
Pages 174 - 179
Abstract
Regarding the communication methods between BMC (Baseboard Management Controller) and CPU, traditional communication methods based on the LPC (Low Pin-Count) interface, such as the KCS (Keyboard Controller Style) communication method, the Serial-Basic communication method based on the serial port, and the SSIF (SMBus System Interface) communication method based on I2C, have the defects of low data transfer rate. This paper proposes a shared memory communication method between BMC and CPU based on PCIE. The software of BMC is designed to allocate a 64KB shared memory area during the startup phase and map the shared memory during the application phase. The software of CPU is designed to query the PCIE device address of BMC and enable its memory space and IO space access rights during the application phase, map the MMIO memory space of PCIE, configure the BMC P2A functional component, and achieve memory sharing. The experiments show that this communication method is stable and reliable, and can effectively improve the data transfer rate between BMC and CPU.
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Index Terms
- PCIE-Based Shared Memory Technology between BMC and CPU
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Published In
December 2023
435 pages
ISBN:9798400716430
DOI:10.1145/3654446
Copyright © 2023 ACM.
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Association for Computing Machinery
New York, NY, United States
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Published: 03 May 2024
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SPCNC 2023
SPCNC 2023: The 2nd International Conference on Signal Processing, Computer Networks and Communications
December 8 - 10, 2023
Xiamen, China
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