A POWER MANAGEMENT CIRCUIT COMPATIBLE with Ti SmartReflex and Xilinx Ultrascale+ MPSoC DUAL VOLTAGE MECHANISM

Since the semiconductor technology has entered the age of 90 nm, the static power consumption of the chip has increased rapidly. For edge computing devices, the waste of power can not be ignored. This paper uses the relationship between power consumption and power supply voltage of FPGA and DSP, analyzes the characteristics of the traditional scheme, and designs a hardware circuit according to the different mechanisms of reducing static power consumption of FPGA and DSP According to the design of FPGA and DSP core power supply voltage compatibility, the system realizes the requirement of FPGA and DSP for power supply voltage amplitude and realizes dynamic control of power supply voltage. After verification and comparison, FPGA and DSP can realize the adjustment of performance power consumption and stable operation under the power system.