SAT-attack Resilience Measure for Access Restricted Circuits
Pages 213 - 220
Abstract
With the recent introduction of techniques to restrict scan chain access, a new class of deobfuscation problems emerge, in which the threat model, although similar to deobfuscation of a logic locked circuit, forms a novel class of attack. In this paper, the concept of a logic restricted circuit is generalized and defined. Next, a novel type of SAT-based attack is proposed for the new class of deobfuscation problems, described as a 2-stage SAT-attack. A SAT-attack resilience measure is developed to quantify the security strength of a logic restricted circuit against a SAT-based attack. Finally, the proposed SAT-resilience framework is applied to compare and evaluate effectiveness of example logic restriction schemes.
Supplemental Material
MP4 File
Pre-recorded presentation video for GLSVLSI 2021 presented by Saran Phatharodom, for the paper with title "SAT-attack Resilience Measure for Access Restricted Circuits", by Saran Phatharodom, Avesta Sasan, and Ioannis Savidis, from Drexel University and George Mason University. The presentation covers (1) definition of logic restriction techniques, (2) security evaluation of a logic restricted circuit against a SAT-based attack, and (3) a comparative case study between a comparator-based restriction scheme and a SARLock-based restriction scheme.
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References
[1]
J. A. Roy, F. Koushanfar, and I. L. Markov, "EPIC: Ending Piracy of Integrated Circuits," Proceedings of the IEEE/ACM Design, Automation & Test in Europe Conference, pp. 1069--1074, Mar. 2008.
[2]
K. Juretus and I. Savidis, "Reduced Overhead Gate Level Logic Encryption, "Proceedings of the IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI), pp. 15--20, May 2016.
[3]
M. Yasin, B. Mazumdar, J. J. V. Rajendran, and O. Sinanoglu, "SARLock: SAT Attack Resistant Logic Locking," Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 236--241, May 2016.
[4]
Y. Xie and A. Srivastava, "Anti-SAT: Mitigating SAT Attack on Logic Locking," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 2, pp. 199--207, Feb. 2019.
[5]
M. Yasin, A. Sengupta, B. C. Schafer, Y. Makris, O. Sinanoglu, and J. J. Rajendran, "What to Lock?: Functional and Parametric Locking," Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, pp. 351--356, May 2017.
[6]
M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. J. Rajendran, and O. Sinanoglu, "Provably-Secure Logic Locking: From Theory To Practice," Proceedings of the ACM SIGSAC Conference on Computer and Communications Security, pp. 1601--1618, Oct. 2017.
[7]
R. S. Chakraborty and S. Bhunia, "HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 10, pp. 1493--1502, Oct. 2009.
[8]
K. Juretus and I. Savidis, "Synthesis of Hidden State Transitions for Sequential Logic Locking," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 40, No. 1, pp. 11--23, Jan. 2021.
[9]
S. Roshanisefat, H. M. Kamali, K. Zamiri Azar, S. M. Pudukotai Dinakarrao, N. Karimi, H. Homayoun, and A. Sasan, "DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain," Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1--6, Apr. 2020.
[10]
M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, "Removal Attacks on Logic Locking and Camouflaging Techniques," IEEE Transactions on Emerging Topics in Computing, Vol. 8, No. 2, pp. 517--532, Aug. 2020.
[11]
D. Sirone and P. Subramanyan, "Functional Analysis Attacks on Logic Locking," IEEE Transactions on Information Forensics and Security, Vol. 15, pp. 2514--2527, Jan. 2020.
[12]
X. Xu, B. Shakya, M. M. Tehranipoor, and D. Forte, "Novel Bypass Attack and BDD-Based Tradeoff Analysis Against All Known Logic Locking Attacks," Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems (CHES), pp. 189--210, Sept. 2017.
[13]
K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, "AppSAT: Approximately Deobfuscating Integrated Circuits," Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 95--100, May 2017.
[14]
Y. Shen and H. Zhou, "Double DIP: Re-Evaluating Security of Logic Encryption Algorithms," Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 179--184, May 2017.
[15]
M. El Massad, S. Garg, and M. Tripunitara, "Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes," Proceedings of the Network and Distributed System Security Symposium (NDSS), pp. 1--14, Feb. 2015.
[16]
P. Subramanyan, S. Ray, and S. Malik, "Evaluating the Security of Logic Encryption Algorithms," Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137--143, May 2015.
[17]
M. El Massad, S. Garg, and M. Tripunitara, "Reverse Engineering Camouflaged Sequential Circuits Without Scan Access," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 33--40, Nov. 2017.
[18]
K. Shamsi, M. Li, D. Z. Pan, and Y. Jin, "KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation," 2019 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 534--539, Mar. 2019.
[19]
R. Karmakar, S. Chattopadhyay, and R. Kapur, "A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, No. 3, pp. 546--550, Mar. 2020.
[20]
Q. L. Nguyen, E. Valea, M. L. Flottes, S. Dupuis, and B. Rouzeyre, "A Secure Scan Controller for Protecting Logic Locking," 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 1--6, July 2020.
[21]
R. Karmakar and S. Chattopadhyay, "On Securing Scan Obfuscation Strategies Against ScanSAT Attack," Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 213--218, Mar. 2020.
[22]
K. Juretus and I. Savidis, "Reducing Logic Locking Key Leakage through the Scan Chain," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1--5, Oct. 2020.
[23]
L. Alrahis, M. Yasin, H. Saleh, B. Mohammad, M. Al-Qutayri, and O. Sinanoglu, "ScanSAT: Unlocking Obfuscated Scan Chains," Proceedings of the Asia and South Pacific Design Automation Conference, p. 352--357, Jan. 2019.
[24]
S. Phatharodom, N. Kandasamy, and I. Savidis, "Modeling SAT-Attack Search Complexity," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1--5, Oct. 2020.
[25]
K. Juretus and I. Savidis, "Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security," Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 366--369, Oct. 2018.
[26]
P. Tuyls, G. Schrijen, B. vS korić, J. van Geloven, N. Verhaegh, and R. Wolters, "Read-Proof Hardware from Protective Coatings," Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems (CHES), pp. 369--383, Oct. 2006.
[27]
M. Yasin and O. Sinanoglu, "Transforming Between Logic Locking and IC Camouflaging," Proceedings of the IEEE International Design for Test Symposium (IDT), pp. 1--4, Dec. 2015.
[28]
Y. Hu, V. V. Menon, A. Schmidt, J. Monson, M. French, and P. Nuzzo, "Security-Driven Metrics and Models for Efficient Evaluation of Logic Encryption Schemes," Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, pp. 1--5, Oct. 2019.
Index Terms
- SAT-attack Resilience Measure for Access Restricted Circuits
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Published In
June 2021
504 pages
ISBN:9781450383936
DOI:10.1145/3453688
- General Chairs:
- Yiran Chen,
- Victor Zhirnov,
- Program Chairs:
- Avesta Sasan,
- Ioannis Savidis
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Published: 22 June 2021
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Pre-recorded presentation video for GLSVLSI 2021 presented by Saran Phatharodom, for the paper with title "SAT-attack Resilience Measure for Access Restricted Circuits", by Saran Phatharodom, Avesta Sasan, and Ioannis Savidis, from Drexel University and George Mason University. The presentation covers (1) definition of logic restriction techniques, (2) security evaluation of a logic restricted circuit against a SAT-based attack, and (3) a comparative case study between a comparator-based restriction scheme and a SARLock-based restriction scheme. https://dl.acm.org/doi/10.1145/3453688.3461759#GLSVLSI21-vlsi62s.mp4
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