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Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)

Author:

Kanad GhoseAuthors Info & Claims

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

Pages 231 - 233

https://doi.org/10.1145/344166.344604

Published: 01 August 2000 Publication History

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Abstract

Recent studies [MGK 98, Tiw 98] have confirmed that a significant amount of energy is dissipated in the process of instruction dispatching and issue in modern superscalar microprocessors. We propose a model for the energy dissipated by instruction dispatching and issuing logic in modern superscalar microprocessors and validate them through register level simulations and SPICE-measured dissipation coefficients from 0.5 micron CMOS layouts of relevant circuits. Alternative organizations are studied for instruction window buffers that result in energy savings of about 47% over traditional designs.

References

[1]

Ghose, K. and Kamble, M.B., "Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation", in Proc. ISLPED '99, pp. 70-75.

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[2]

Manne, S., Grunwald, D., and Klauser, A. "Pipeline gating: speculation control for energy reduction", in Proc. 25-th Int'l. Sym. on Computer ARchitecture, pp. 132-141, 1998.

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[3]

Palacharla, S., J ouppi, N. E and Smith, J.E., "Quantifying the complexity of superscalar processors", Technical report CS- TR-96-1308, Dept. of CS, Univ. of Wisconsin, 1996.

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[4]

, Tiwari V., et al., "Reducing power in high-performance microprocessors", in Proc. Design Automation Conf., 1198, pp. 732-737.

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Vasseghi, N. et al, "200 MHz. Superscalar RISC processor circuit design issues", Proc. ISSCC digest of technical papers, 1996, pp. 356-357.

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Cited By

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Kumar CMadhavi BKishore K(2012)Optimal Designing Approach to Recursive Coding in VLSI DesignProceedings of the 2012 International Conference on Advances in Mobile Network, Communication and Its Applications10.1109/MNCApps.2012.11(29-33)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1109/MNCApps.2012.11
Mahjur ATaghizadeh MJahangir ANarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Lazy instruction schedulingProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1394020(375-380)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1394020
Soundararajan NYanamandra ANicopoulos CVijaykrishnan NSivasubramaniam AIrwin M(2008)Analysis and solutions to issue queue process variation2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)10.1109/DSN.2008.4630066(11-21)Online publication date: Jun-2008
https://doi.org/10.1109/DSN.2008.4630066
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Index Terms

Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Information & Contributors

Information

Published In

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

August 2000

313 pages

ISBN:1581131909

DOI:10.1145/344166

Editors:
David Blaauw
Motorola, Inc., Austin, TX
,
Christian Enz
CSEM, Maladière, Switzerland
,
Thad Gabara
Lucent Technologies
,
Enrico Macii
Politenico di Torino, Turin, Italy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 2000

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ISLPED00

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SIGDA
IEEE-CAS

ISLPED00: International Symposium on Low Power Electronic Design

July 25 - 27, 2000

Rapallo, Italy

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Kumar CMadhavi BKishore K(2012)Optimal Designing Approach to Recursive Coding in VLSI DesignProceedings of the 2012 International Conference on Advances in Mobile Network, Communication and Its Applications10.1109/MNCApps.2012.11(29-33)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1109/MNCApps.2012.11
Mahjur ATaghizadeh MJahangir ANarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Lazy instruction schedulingProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1394020(375-380)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1394020
Soundararajan NYanamandra ANicopoulos CVijaykrishnan NSivasubramaniam AIrwin M(2008)Analysis and solutions to issue queue process variation2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)10.1109/DSN.2008.4630066(11-21)Online publication date: Jun-2008
https://doi.org/10.1109/DSN.2008.4630066
Mesa-Martínez FHuang MRenau JAltman ESkadron KZorn B(2006)SEEDProceedings of the 15th international conference on Parallel architectures and compilation techniques10.1145/1152154.1152193(254-264)Online publication date: 16-Sep-2006
https://dl.acm.org/doi/10.1145/1152154.1152193
Ponomarev DKucuk GErgin OGhose KKogge P(2003)Energy-efficient issue queue designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81432111:5(789-800)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.814321
Dropsho SKursun VAlbonesi DDwarkadas SFriedman EAltman EEbcioǧlu KMahlke SRau BPatel S(2002)Managing static leakage energy in microprocessor functional unitsProceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture10.5555/774861.774896(321-332)Online publication date: 18-Nov-2002
https://dl.acm.org/doi/10.5555/774861.774896
Huang MRenau JTorrellas JDe VIrwin MVerbauwhede IPiguet C(2002)Energy-efficient hybrid wakeup logicProceedings of the 2002 international symposium on Low power electronics and design10.1145/566408.566456(196-201)Online publication date: 12-Aug-2002
https://dl.acm.org/doi/10.1145/566408.566456
Kucuk GGhose KPonomarev DKogge PMacii EDe VIrwin M(2001)EnergyProceedings of the 2001 international symposium on Low power electronics and design10.1145/383082.383144(237-242)Online publication date: 6-Aug-2001
https://dl.acm.org/doi/10.1145/383082.383144

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