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Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis

Published: 07 September 2020 Publication History

Abstract

With the downscaling of CMOS technology, the circuit design margin becomes more and more tight due to wider guardband, which is required to counteract the severer transistor aging and variations. Thus, reliability-enhanced circuit design is urgently needed to reduce the guardband. In this paper, a reliability-enhanced design framework based on approximate synthesis is proposed to completely eliminate the aging guardband. It mainly includes two key parts: first, a forward reliability simulation flow supporting statistical static timing analysis (SSTA) is performed to estimate the path failure rates after aging; if the timing constraints are not satisfied, then a backward delay-driven approximate logic synthesis flow will perform approximate local changes on the critical paths to reduce the delay until the reliability requirement is finally satisfied and no aging guardband is needed. The results show that the approximate circuit has a smaller aged delay than the original circuit, so that the path failure rates are significantly decreased. It indicates that the proposed design flow can convert the timing errors that have fatal impact on applications, into negligible error on low-significance bits to improve the resilience of circuits, which provides a new perspective of reliability-enhanced design at nanoscale.

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References

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Cited By

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  • (2023)Logical Resolving-Based Methodology for Efficient Reliability AnalysisMicromachines10.3390/mi1501008515:1(85)Online publication date: 30-Dec-2023
  • (2023)Data-Driven Feature Selection Framework for Approximate Circuit DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326016042:11(3519-3531)Online publication date: Nov-2023
  • (2023)AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient ComputingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325516742:11(4139-4151)Online publication date: Nov-2023
  • Show More Cited By

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Information

Published In

cover image ACM Other conferences
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
September 2020
597 pages
ISBN:9781450379441
DOI:10.1145/3386263
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 September 2020

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Author Tags

  1. aging
  2. approximate computing
  3. circuit reliability simulation
  4. guardband
  5. logic synthesis
  6. negative bias temperature instability (NBTI)
  7. reliability-enhanced design
  8. statistical static timing analysis (SSTA)

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  • Research-article

Funding Sources

  • the National Key R&D Program of China
  • NSFC
  • 111 Project

Conference

GLSVLSI '20
GLSVLSI '20: Great Lakes Symposium on VLSI 2020
September 7 - 9, 2020
Virtual Event, China

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2023)Logical Resolving-Based Methodology for Efficient Reliability AnalysisMicromachines10.3390/mi1501008515:1(85)Online publication date: 30-Dec-2023
  • (2023)Data-Driven Feature Selection Framework for Approximate Circuit DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326016042:11(3519-3531)Online publication date: Nov-2023
  • (2023)AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient ComputingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325516742:11(4139-4151)Online publication date: Nov-2023
  • (2022)EventTimerProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540065(945-950)Online publication date: 14-Mar-2022
  • (2022)EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774642(945-950)Online publication date: 14-Mar-2022
  • (2022)Variability-Aware Approximate Circuit Synthesis via Genetic OptimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.318385869:10(4141-4153)Online publication date: Oct-2022
  • (2021)Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?2021 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS46558.2021.9405167(1-7)Online publication date: 21-Mar-2021

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