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The challenge of multi-operand adders in CNNs on FPGAs: how not to solve it!

Published: 15 July 2018 Publication History

Abstract

Convolutional Neural Networks (CNNs) are computationally intensive algorithms that currently require dedicated hardware to be executed. In the case of FPGA-Based accelerators, we point-out in this work the challenge of Multi-Operand Adders (MOAs) and their high resource utilization in an FPGA implementation of a CNN. To address this challenge, two optimization strategies, that rely on time-multiplexing and approximate computing, are investigated. At first glance, the two strategies looked promising to reduce the footprint of a given architectural mapping, but when synthesized on the device, none of them gave the expected results. Experimental sections analyze the reasons of these unexpected results.

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  • (2023)Efficient Multipliers for CNN with Optimized Compression Techniques2023 20th International Bhurban Conference on Applied Sciences and Technology (IBCAST)10.1109/IBCAST59916.2023.10713003(291-296)Online publication date: 22-Aug-2023
  • (2022)Vedic Multiplier and Wallace Tree Adders Based Optimised Processing Element Unit for CNN on FPGA2022 IEEE International Power and Renewable Energy Conference (IPRECON)10.1109/IPRECON55716.2022.10059532(1-6)Online publication date: 16-Dec-2022
  • (2022)Energy-Efficient Approximate Booth Multipliers for Convolutional Neural Networks2022 19th International Bhurban Conference on Applied Sciences and Technology (IBCAST)10.1109/IBCAST54850.2022.9990150(268-272)Online publication date: 16-Aug-2022
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    cover image ACM Other conferences
    SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
    July 2018
    263 pages
    ISBN:9781450364942
    DOI:10.1145/3229631
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 15 July 2018

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    Author Tags

    1. CNN
    2. FPGA
    3. adder trees
    4. approximate computing

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    • Short-paper

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    SAMOS XVIII
    SAMOS XVIII: Architectures, Modeling, and Simulation
    July 15 - 19, 2018
    Pythagorion, Greece

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    Cited By

    View all
    • (2023)Efficient Multipliers for CNN with Optimized Compression Techniques2023 20th International Bhurban Conference on Applied Sciences and Technology (IBCAST)10.1109/IBCAST59916.2023.10713003(291-296)Online publication date: 22-Aug-2023
    • (2022)Vedic Multiplier and Wallace Tree Adders Based Optimised Processing Element Unit for CNN on FPGA2022 IEEE International Power and Renewable Energy Conference (IPRECON)10.1109/IPRECON55716.2022.10059532(1-6)Online publication date: 16-Dec-2022
    • (2022)Energy-Efficient Approximate Booth Multipliers for Convolutional Neural Networks2022 19th International Bhurban Conference on Applied Sciences and Technology (IBCAST)10.1109/IBCAST54850.2022.9990150(268-272)Online publication date: 16-Aug-2022
    • (2020)Power Efficient Tiny Yolo CNN using Reduced Hardware Resources based on Booth Multiplier and WALLACE Tree AddersIEEE Open Journal of Circuits and Systems10.1109/OJCAS.2020.3007334(1-1)Online publication date: 2020
    • (2020)Bit-Serial multiplier based Neural Processing Element with Approximate adder tree2020 International SoC Design Conference (ISOCC)10.1109/ISOCC50952.2020.9332993(286-287)Online publication date: 21-Oct-2020
    • (2020)RETRACTED ARTICLE: A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGAJournal of Ambient Intelligence and Humanized Computing10.1007/s12652-020-02402-312:7(7263-7271)Online publication date: 7-Aug-2020
    • (2019)Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00019(55-60)Online publication date: Jul-2019
    • (2019)A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702777(1-4)Online publication date: May-2019
    • (2019)Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light DetectionIEEE Access10.1109/ACCESS.2019.29590847(178167-178176)Online publication date: 2019
    • (2019)Design of Hardware Accelerator for Artificial Neural Networks Using Multi-operand AdderInformation, Communication and Computing Technology10.1007/978-981-15-1384-8_14(167-177)Online publication date: 13-Nov-2019

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